thirdparty/ppsspp
2
0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

ARM64: Fix FCVTL, use it in v2hf

Browse source
This commit is contained in:
Henrik Rydgard 2015-03-22 22:42:33 +01:00
parent 8eedcc7fb0
commit acf08eefa8
6 changed files with 115 additions and 37 deletions
Download patch file Download diff file Expand all files Collapse all files

5
Core/Util/DisArm64.cpp
View file

@ -428,7 +428,8 @@ static void FPandASIMD1(uint32_t w, uint64_t addr, Instruction *instr) {
break;
case 2:
if (((w >> 17) & 0xf) == 0) {
snprintf(instr->text, sizeof(instr->text), "(asimd two-reg misc %08x)", w);
// Very similar to scalar two-reg misc. can we share code?
snprintf(instr->text, sizeof(instr->text), "(asimd vector two-reg misc %08x)", w);
} else if (((w >> 17) & 0xf) == 1) {
snprintf(instr->text, sizeof(instr->text), "(asimd across lanes %08x)", w);
} else {
@ -463,7 +464,7 @@ static void FPandASIMD1(uint32_t w, uint64_t addr, Instruction *instr) {
}
int index;
if ((size & 1) == 0) {
index = (H << 1) | L;
index = (H << 1) | (int)L;
} else {
index = H;
}