thirdparty/ppsspp
2
0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

x86jit: Add Vec4 and Float load/store.

Browse source
This commit is contained in:
Unknown W. Brackets 2023-08-21 23:23:59 -07:00 • committed by Henrik Rydgård
parent 951c35ba71
commit edcb156897
4 changed files with 30 additions and 7 deletions
Download patch file Download diff file Expand all files Collapse all files

2
Core/MIPS/IR/IRRegCache.cpp
View file

@ -907,7 +907,7 @@ void IRNativeRegCacheBase::MapNativeReg(MIPSLoc type, IRNativeReg nreg, IRReg fi
}
// If it's still in a different reg, either discard or possibly transfer.
if (mreg.nReg != -1 && mreg.nReg != nreg) {
if (mreg.nReg != -1 && (mreg.nReg != nreg || mismatch)) {
_assert_msg_(!mreg.isStatic, "Cannot MapNativeReg a static reg to a new reg");
if ((flags & MIPSMap::NOINIT) != MIPSMap::NOINIT) {
// We better not be trying to map to a different nreg if it's in one now.

20
Core/MIPS/x86/X64IRCompLoadStore.cpp
View file

@ -90,9 +90,12 @@ void X64JitBackend::CompIR_CondStore(IRInst inst) {
void X64JitBackend::CompIR_FLoad(IRInst inst) {
CONDITIONAL_DISABLE;
OpArg addrArg = PrepareSrc1Address(inst);
switch (inst.op) {
case IROp::LoadFloat:
CompIR_Generic(inst);
regs_.MapFPR(inst.dest, MIPSMap::NOINIT);
MOVSS(regs_.FX(inst.dest), addrArg);
break;
default:
@ -104,9 +107,12 @@ void X64JitBackend::CompIR_FLoad(IRInst inst) {
void X64JitBackend::CompIR_FStore(IRInst inst) {
CONDITIONAL_DISABLE;
OpArg addrArg = PrepareSrc1Address(inst);
switch (inst.op) {
case IROp::StoreFloat:
CompIR_Generic(inst);
regs_.MapFPR(inst.src3);
MOVSS(addrArg, regs_.FX(inst.dest));
break;
default:
@ -241,9 +247,12 @@ void X64JitBackend::CompIR_StoreShift(IRInst inst) {
void X64JitBackend::CompIR_VecLoad(IRInst inst) {
CONDITIONAL_DISABLE;
OpArg addrArg = PrepareSrc1Address(inst);
switch (inst.op) {
case IROp::LoadVec4:
CompIR_Generic(inst);
regs_.MapVec4(inst.dest, MIPSMap::NOINIT);
MOVUPS(regs_.FX(inst.dest), addrArg);
break;
default:
@ -255,9 +264,12 @@ void X64JitBackend::CompIR_VecLoad(IRInst inst) {
void X64JitBackend::CompIR_VecStore(IRInst inst) {
CONDITIONAL_DISABLE;
OpArg addrArg = PrepareSrc1Address(inst);
switch (inst.op) {
case IROp::StoreVec4:
CompIR_Generic(inst);
regs_.MapVec4(inst.src3);
MOVUPS(addrArg, regs_.FX(inst.dest));
break;
default:

14
Core/MIPS/x86/X64IRRegCache.cpp
View file

@ -35,9 +35,8 @@ using namespace X64IRJitConstants;
X64IRRegCache::X64IRRegCache(MIPSComp::JitOptions *jo)
: IRNativeRegCacheBase(jo) {
// TODO: Enable SIMD.
config_.totalNativeRegs = NUM_X_REGS + NUM_X_FREGS;
config_.mapFPUSIMD = false;
config_.mapFPUSIMD = true;
// XMM regs are used for both FPU and Vec, so we don't need VREGs.
config_.mapUseVRegs = false;
}
@ -191,6 +190,17 @@ X64Reg X64IRRegCache::MapFPR(IRReg mipsReg, MIPSMap mapFlags) {
return INVALID_REG;
}
X64Reg X64IRRegCache::MapVec4(IRReg first, MIPSMap mapFlags) {
_dbg_assert_(IsValidFPR(mipsReg));
_dbg_assert_((mipsReg & 3) == 0);
_dbg_assert_(mr[mipsReg + 32].loc == MIPSLoc::MEM || mr[mipsReg + 32].loc == MIPSLoc::FREG);
IRNativeReg nreg = MapNativeReg(MIPSLoc::FREG, first + 32, 4, mapFlags);
if (nreg != -1)
return FromNativeReg(nreg);
return INVALID_REG;
}
void X64IRRegCache::AdjustNativeRegAsPtr(IRNativeReg nreg, bool state) {
_assert_(nreg >= 0 && nreg < NUM_X_REGS);
X64Reg r = FromNativeReg(nreg);

1
Core/MIPS/x86/X64IRRegCache.h
View file

@ -73,6 +73,7 @@ public:
Gen::X64Reg MapGPR(IRReg reg, MIPSMap mapFlags = MIPSMap::INIT);
Gen::X64Reg MapGPRAsPointer(IRReg reg);
Gen::X64Reg MapFPR(IRReg reg, MIPSMap mapFlags = MIPSMap::INIT);
Gen::X64Reg MapVec4(IRReg first, MIPSMap mapFlags = MIPSMap::INIT);
Gen::X64Reg MapWithFPRTemp(IRInst &inst);