313 lines
10 KiB
C++
313 lines
10 KiB
C++
// Copyright (c) 2015- PPSSPP Project.
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, version 2.0 or later versions.
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License 2.0 for more details.
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// A copy of the GPL 2.0 should have been included with the program.
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// If not, see http://www.gnu.org/licenses/
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// Official git repository and contact information can be found at
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// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
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// Basic ARM64 disassembler.
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// No promises of accuracy, mostly just made to debug JIT code.
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// Contains just enough to sort of understand what's going on without having to resort to an
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// external disassembler all the time...
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#include <stdlib.h>
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#include "Common/Arm64Emitter.h"
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#include "Common/StringUtils.h"
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struct Instruction {
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char text[128];
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bool undefined;
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bool badbits;
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bool oddbits;
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};
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int SignExtend26(int x) {
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return (x & 0x02000000) ? (0xFC000000 | x) : (x & 0x3FFFFFF);
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}
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int SignExtend19(int x) {
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return (x & 0x00040000) ? (0xFFF80000 | x) : (x & 0x7FFFF);
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}
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int SignExtend9(int x) {
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return (x & 0x00000100) ? (0xFFFFFE00 | x) : (x & 0x1FF);
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}
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int SignExtend12(int x) {
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return (x & 0x00000800) ? (0xFFFFF000 | x) : (x & 0xFFF);
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}
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static const char *conds[16] = {
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"eq", // Equal
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"ne", // Not equal
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"cs", // Carry Set "HS"
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"cc", // Carry Clear "LO"
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"mi", // Minus (Negative)
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"pl", // Plus
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"vs", // Overflow
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"vc", // No Overflow
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"hi", // Unsigned higher
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"ls", // Unsigned lower or same
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"ge", // Signed greater than or equal
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"lt", // Signed less than
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"gt", // Signed greater than
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"le", // Signed less than or equal
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"al", // Always (unconditional) 14
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};
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static void DataProcessingImmediate(uint32_t w, uint64_t addr, Instruction *instr) {
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int Rd = w & 0x1f;
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int Rn = (w >> 5) & 0x1f;
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char r = ((w >> 31) & 1) ? 'x' : 'w';
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if (((w >> 23) & 0x3f) == 0x25) {
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// Constant initialization.
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int imm16 = (w >> 5) & 0xFFFF;
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int opc = (w >> 29) & 3;
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int shift = ((w >> 21) & 0x3) * 16;
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const char *opnames[4] = { "movn", "(undef)", "movz", "movk" };
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snprintf(instr->text, sizeof(instr->text), "%s %c%d, 0x%04x << %d", opnames[opc], r, Rd, imm16, shift);
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} else if (((w >> 24) & 0x1F) == 0x10) {
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// Address generation relative to PC
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int op = w >> 31;
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int imm = SignExtend19(w >> 5);
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if (op & 1) imm <<= 12;
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u64 daddr = addr + imm;
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snprintf(instr->text, sizeof(instr->text), "%s x%d, 0x%04x%08x", op ? "adrp" : "adr", Rd, daddr >> 32, daddr & 0xFFFFFFFF);
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} else if (((w >> 24) & 0x1F) == 0x11) {
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// Add/subtract immediate value
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int op = (w >> 30) & 1;
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int imm = ((w >> 10) & 0xFFF);
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int shift = ((w >> 22) & 0x3) * 16;
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imm <<= shift;
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snprintf(instr->text, sizeof(instr->text), "%s %c%d, %c%d, %d", op == 0 ? "add" : "sub", r, Rd, r, Rn, imm);
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} else {
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snprintf(instr->text, sizeof(instr->text), "(DPI %08x)", w);
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}
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}
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static void BranchExceptionAndSystem(uint32_t w, uint64_t addr, Instruction *instr) {
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int Rt = w & 0x1f;
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int Rn = (w >> 5) & 0x1f;
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if (((w >> 26) & 0x1F) == 5) {
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// Unconditional branch / branch+link
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int offset = SignExtend26(w) << 2;
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uint64_t target = addr + offset;
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snprintf(instr->text, sizeof(instr->text), "b%s %04x%08x", (w >> 31) ? "l" : "", (target >> 32), (target & 0xFFFFFFFF));
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} else if (((w >> 25) & 0x3F) == 0x1A) {
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// Compare and branch
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int op = (w >> 24) & 1;
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const char *opname[2] = { "cbz", "cbnz" };
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char r = ((w >> 31) & 1) ? 'x' : 'w';
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int offset = SignExtend19(w >> 5);
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snprintf(instr->text, sizeof(instr->text), "%s %c%d", op, r, Rt);
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} else if (((w >> 25) & 0x3F) == 0x1B) {
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// Test and branch
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snprintf(instr->text, sizeof(instr->text), "(test & branch %08x)", w);
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} else if (((w >> 25) & 0x7F) == 0x2A) {
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// Conditional branch
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int offset = SignExtend19(w >> 5) << 2;
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uint64_t target = addr + offset;
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int cond = w & 0xF;
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snprintf(instr->text, sizeof(instr->text), "b.%s %04x08x", conds[cond], (target >> 32), (target & 0xFFFFFFFF));
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} else if ((w >> 24) == 0xD4) {
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snprintf(instr->text, sizeof(instr->text), "(exception-gen %08x)", w);
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} else if (((w >> 20) & 0xFFC) == 0xD50) {
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snprintf(instr->text, sizeof(instr->text), "(system-reg %08x)", w);
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} else if (((w >> 25) & 0x7F) == 0x6B) {
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int op = (w >> 21) & 3;
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const char *opname[4] = { "b", "bl", "ret", "(unk)" };
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snprintf(instr->text, sizeof(instr->text), "%s x%d", opname[op], Rn);
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} else {
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snprintf(instr->text, sizeof(instr->text), "(BRX ?? %08x)", w);
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}
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}
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static void LoadStore(uint32_t w, uint64_t addr, Instruction *instr) {
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int size = w >> 30;
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int imm9 = SignExtend9((w >> 12) & 0x1FF);
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int Rt = (w & 0x1F);
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int Rn = ((w >> 5) & 0x1F);
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int Rm = ((w >> 16) & 0x1F);
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int option = (w >> 13) & 0x7;
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int opc = (w >> 22) & 0x3;
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char r = size == 3 ? 'x' : 'w';
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const char *opname[4] = { "str", "ldr", "str", "ldr" };
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const char *sizeSuffix[4] = { "b", "w", "", "" };
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if (((w >> 21) & 1) == 1) {
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// register offset
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snprintf(instr->text, sizeof(instr->text), "%s%s %c%d, [x%d + w%d]", opname[opc], sizeSuffix[size], r, Rt, Rn, Rm);
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return;
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} else if (((w >> 27) & 7) == 7) {
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int V = (w >> 26) & 1;
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bool index_unsigned = ((w >> 24) & 3) == 1;
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int imm12 = SignExtend12((w >> 10) & 0xFFF) << size;
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if (V == 0) {
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// Integer type
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if (index_unsigned) {
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snprintf(instr->text, sizeof(instr->text), "%s%s %c%d, [x%d + %d]", opname[opc], sizeSuffix[size], r, Rt, Rn, imm12);
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return;
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}
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} else {
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// FP/Vector type
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char vr = '!';
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if (opc == 3 && size == 0) {
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vr = 'q';
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} else {
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vr = "bhsd"[size];
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}
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if (index_unsigned) {
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snprintf(instr->text, sizeof(instr->text), "%s %c%d, [x%d + %d]", opname[opc], vr, Rt, Rn, imm12);
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return;
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}
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}
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}
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snprintf(instr->text, sizeof(instr->text), "(LS %08x)", w);
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}
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static void DataProcessingRegister(uint32_t w, uint64_t addr, Instruction *instr) {
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int Rd = w & 0x1F;
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int Rn = (w >> 5) & 0x1F;
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int Rm = (w >> 16) & 0x1F;
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char r = ((w >> 31) & 1) ? 'x' : 'w';
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if (((w >> 21) & 0xF) == 9) {
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bool S = (w >> 29) & 1;
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bool sub = (w >> 30) & 1;
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if (Rd == 31 && S) {
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// It's a CMP
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snprintf(instr->text, sizeof(instr->text), "%s%s %c%d, %c%d", "cmp", S ? "s" : "", r, Rn, r, Rm);
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} else {
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snprintf(instr->text, sizeof(instr->text), "%s%s %c%d, %c%d, %c%d", sub ? "sub" : "add", S ? "s" : "", r, Rd, r, Rn, r, Rm);
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}
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} else if (((w >> 21) & 0x2FF) == 0x2D6) {
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// Data processing
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int opcode2 = (w >> 16) & 0x1F;
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if (opcode2 == 0) {
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int opcode = (w >> 10) & 0x3F;
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// Data-processing (1 source)
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const char *opname[8] = { "rbit", "rev16", "rev", "(unk)", "clz", "cls" };
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const char *op = opcode2 >= 8 ? "unk" : opname[opcode];
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snprintf(instr->text, sizeof(instr->text), "%s %c%d, %c%d", op, r, Rn, r, Rm);
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} else {
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// Data processing (2 source)
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snprintf(instr->text, sizeof(instr->text), "(data-proc-2-source %08x)", w);
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}
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} else if (((w >> 24) & 0x1f) == 0xA) {
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// Logical (shifted register)
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int shift = (w >> 22) & 0x3;
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int imm6 = (w >> 10) & 0x3f;
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int N = (w >> 21) & 1;
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int opc = (((w >> 29) & 3) << 1) | N;
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const char *opnames[8] = { "and", "bic", "orr", "orn", "eor", "eon", "ands", "bics" };
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if (opc == 3 && Rn == 31) {
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// Special case for MOV (which is constructed from an ORR)
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snprintf(instr->text, sizeof(instr->text), "%s %c%d, %c%d", opnames[opc], r, Rd, r, Rm);
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} else if (imm6 == 0) {
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snprintf(instr->text, sizeof(instr->text), "%s %c%d, %c%d, %c%d", opnames[opc], r, Rd, r, Rn, r, Rm);
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} else {
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snprintf(instr->text, sizeof(instr->text), "(logical-shifted-register %08x", w);
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}
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} else {
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snprintf(instr->text, sizeof(instr->text), "(DPR %08x)", w);
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}
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}
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static void FPandASIMD1(uint32_t w, uint64_t addr, Instruction *instr) {
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snprintf(instr->text, sizeof(instr->text), "(FP1 %08x)", w);
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}
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static void FPandASIMD2(uint32_t w, uint64_t addr, Instruction *instr) {
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int Rd = w & 0x1f;
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int Rn = (w >> 5) & 0x1f;
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int Rm = (w >> 16) & 0x1f;
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int type = (w >> 22) & 0x3;
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if ((w >> 24) == 0x1E) {
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if (((w >> 10) & 0x39f) == 0x810) {
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const char *opnames[4] = { "fmov", "fabs", "fneg", "fsqrt" };
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int opc = (w >> 15) & 0x3;
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snprintf(instr->text, sizeof(instr->text), "%s !%d, !%d (%08x)", opnames[opc], Rd, Rn, w);
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} else if (((w >> 10) & 3) == 2) {
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// FP data-proc (2 source)
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int opc = (w >> 12) & 0xf;
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if (type == 0 || type == 1) {
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const char *opnames[9] = { "fmul", "fdiv", "fadd", "fsub", "fmax", "fmin", "fmaxnm", "fminnm", "fnmul" };
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char r = 's';
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snprintf(instr->text, sizeof(instr->text), "%s %c%d, %c%d, %c%d", opnames[opc], r, Rd, r, Rn, r, Rm);
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} else {
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snprintf(instr->text, sizeof(instr->text), "(FP2 %08x)", w);
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}
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}
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} else {
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snprintf(instr->text, sizeof(instr->text), "(FP2 %08x)", w);
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}
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}
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static void DisassembleInstruction(uint32_t w, uint64_t addr, Instruction *instr) {
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memset(instr, 0, sizeof(*instr));
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// Identify the main encoding groups. See C3.1 A64 instruction index by encoding
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int id = (w >> 25) & 0xF;
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switch (id) {
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case 0: case 1: case 2: case 3: // 00xx
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instr->undefined = true;
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break;
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case 8: case 9:
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DataProcessingImmediate(w, addr, instr);
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break;
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case 0xA: case 0xB:
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BranchExceptionAndSystem(w, addr, instr);
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break;
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case 4: case 6: case 0xC: case 0xE:
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LoadStore(w, addr, instr);
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break;
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case 5: case 0xD:
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DataProcessingRegister(w, addr, instr);
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break;
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case 7:
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FPandASIMD1(w, addr, instr);
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break;
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case 0xF:
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FPandASIMD2(w, addr, instr);
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break;
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}
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}
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void Arm64Dis(uint64_t addr, uint32_t w, char *output, int bufsize, bool includeWord) {
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Instruction instr;
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DisassembleInstruction(w, addr, &instr);
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char temp[256];
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if (includeWord) {
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snprintf(output, bufsize, "%08x\t%s", w, instr.text);
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} else {
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snprintf(output, bufsize, "%s", instr.text);
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}
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if (instr.undefined || instr.badbits || instr.oddbits) {
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if (instr.undefined) snprintf(output, bufsize, "%08x\t[undefined instr]", w);
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if (instr.badbits) snprintf(output, bufsize, "%08x\t[illegal bits]", w);
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// strcat(output, " ? (extra bits)");
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if (instr.oddbits) {
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snprintf(temp, sizeof(temp), " [unexpected bits %08x]", w);
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strcat(output, temp);
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}
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}
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// zap tabs
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while (*output) {
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if (*output == '\t')
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*output = ' ';
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output++;
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}
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}
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