688 lines
25 KiB
C++
688 lines
25 KiB
C++
// Copyright (c) 2013- PPSSPP Project.
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, version 2.0 or later versions.
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License 2.0 for more details.
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// A copy of the GPL 2.0 should have been included with the program.
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// If not, see http://www.gnu.org/licenses/
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// Official git repository and contact information can be found at
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// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
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#include "base/logging.h"
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#include "Common/CPUDetect.h"
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#include "Core/Config.h"
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#include "Core/Reporting.h"
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#include "Common/Arm64Emitter.h"
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#include "Core/MIPS/JitCommon/JitCommon.h"
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#include "GPU/GPUState.h"
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#include "GPU/Common/VertexDecoderCommon.h"
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static float MEMORY_ALIGNED16(bones[16 * 8]); // First two are kept in registers
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static float MEMORY_ALIGNED16(boneMask[4]) = {1.0f, 1.0f, 1.0f, 0.0f};
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static const float by128 = 1.0f / 128.0f;
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static const float by16384 = 1.0f / 16384.0f;
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static const float by32768 = 1.0f / 32768.0f;
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using namespace Arm64Gen;
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// Pointers, X regs
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static const ARM64Reg srcReg = X0;
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static const ARM64Reg dstReg = X1;
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static const ARM64Reg counterReg = W2;
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static const ARM64Reg tempReg1 = W3;
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static const ARM64Reg tempRegPtr = X3;
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static const ARM64Reg tempReg2 = W4;
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static const ARM64Reg tempReg3 = W5;
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static const ARM64Reg scratchReg = W6;
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static const ARM64Reg scratchReg2 = W7;
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static const ARM64Reg scratchReg3 = W8;
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static const ARM64Reg fullAlphaReg = W12;
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static const ARM64Reg fpScratchReg = S4;
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static const ARM64Reg fpScratchReg2 = S5;
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static const ARM64Reg fpScratchReg3 = S6;
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static const ARM64Reg fpScratchReg4 = S7;
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static const ARM64Reg fpUVscaleReg = D0;
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static const ARM64Reg fpUVoffsetReg = D1;
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static const ARM64Reg neonScratchReg = D2;
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static const ARM64Reg neonScratchReg2 = D3;
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static const ARM64Reg neonScratchRegQ = Q2;
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static const ARM64Reg neonUVScaleReg = D0;
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static const ARM64Reg neonUVOffsetReg = D1;
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static const ARM64Reg src[3] = {Q2, Q3, Q8};
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static const ARM64Reg srcNEON = Q8;
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static const ARM64Reg accNEON = Q9;
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static const ARM64Reg neonWeightRegsQ[2] = { Q2, Q3 };
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// Q4-Q7 is the generated matrix that we multiply things by.
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// Q8,Q9 are accumulators/scratch for matrix mul.
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// Q10, Q11 are more scratch for matrix mul.
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// Q16+ are free-for-all for matrices. In 16 registers, we can fit 4 4x4 matrices.
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static const JitLookup jitLookup[] = {
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{&VertexDecoder::Step_WeightsU8, &VertexDecoderJitCache::Jit_WeightsU8},
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{&VertexDecoder::Step_WeightsU16, &VertexDecoderJitCache::Jit_WeightsU16},
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{&VertexDecoder::Step_WeightsFloat, &VertexDecoderJitCache::Jit_WeightsFloat},
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{&VertexDecoder::Step_WeightsU8Skin, &VertexDecoderJitCache::Jit_WeightsU8Skin},
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{&VertexDecoder::Step_WeightsU16Skin, &VertexDecoderJitCache::Jit_WeightsU16Skin},
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{&VertexDecoder::Step_WeightsFloatSkin, &VertexDecoderJitCache::Jit_WeightsFloatSkin},
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{&VertexDecoder::Step_TcU8, &VertexDecoderJitCache::Jit_TcU8},
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{&VertexDecoder::Step_TcU16, &VertexDecoderJitCache::Jit_TcU16},
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{&VertexDecoder::Step_TcFloat, &VertexDecoderJitCache::Jit_TcFloat},
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{&VertexDecoder::Step_TcU16Double, &VertexDecoderJitCache::Jit_TcU16Double},
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{&VertexDecoder::Step_TcU8Prescale, &VertexDecoderJitCache::Jit_TcU8Prescale},
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{&VertexDecoder::Step_TcU16Prescale, &VertexDecoderJitCache::Jit_TcU16Prescale},
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{&VertexDecoder::Step_TcFloatPrescale, &VertexDecoderJitCache::Jit_TcFloatPrescale},
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{&VertexDecoder::Step_TcU16Through, &VertexDecoderJitCache::Jit_TcU16Through},
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{&VertexDecoder::Step_TcFloatThrough, &VertexDecoderJitCache::Jit_TcFloatThrough},
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{&VertexDecoder::Step_TcU16ThroughDouble, &VertexDecoderJitCache::Jit_TcU16ThroughDouble},
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{&VertexDecoder::Step_NormalS8, &VertexDecoderJitCache::Jit_NormalS8},
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{&VertexDecoder::Step_NormalS16, &VertexDecoderJitCache::Jit_NormalS16},
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{&VertexDecoder::Step_NormalFloat, &VertexDecoderJitCache::Jit_NormalFloat},
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{&VertexDecoder::Step_NormalS8Skin, &VertexDecoderJitCache::Jit_NormalS8Skin},
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{&VertexDecoder::Step_NormalS16Skin, &VertexDecoderJitCache::Jit_NormalS16Skin},
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{&VertexDecoder::Step_NormalFloatSkin, &VertexDecoderJitCache::Jit_NormalFloatSkin},
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{&VertexDecoder::Step_Color8888, &VertexDecoderJitCache::Jit_Color8888},
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/*
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{&VertexDecoder::Step_Color4444, &VertexDecoderJitCache::Jit_Color4444},
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{&VertexDecoder::Step_Color565, &VertexDecoderJitCache::Jit_Color565},
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{&VertexDecoder::Step_Color5551, &VertexDecoderJitCache::Jit_Color5551},
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{&VertexDecoder::Step_PosS8Through, &VertexDecoderJitCache::Jit_PosS8Through},
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*/
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{&VertexDecoder::Step_PosS16Through, &VertexDecoderJitCache::Jit_PosS16Through},
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/*
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{&VertexDecoder::Step_PosFloatThrough, &VertexDecoderJitCache::Jit_PosFloat},
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*/
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{&VertexDecoder::Step_PosS8, &VertexDecoderJitCache::Jit_PosS8},
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{&VertexDecoder::Step_PosS16, &VertexDecoderJitCache::Jit_PosS16},
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{&VertexDecoder::Step_PosFloat, &VertexDecoderJitCache::Jit_PosFloat},
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{&VertexDecoder::Step_PosS8Skin, &VertexDecoderJitCache::Jit_PosS8Skin},
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{&VertexDecoder::Step_PosS16Skin, &VertexDecoderJitCache::Jit_PosS16Skin},
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{&VertexDecoder::Step_PosFloatSkin, &VertexDecoderJitCache::Jit_PosFloatSkin},
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/*
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{&VertexDecoder::Step_NormalS8Morph, &VertexDecoderJitCache::Jit_NormalS8Morph},
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{&VertexDecoder::Step_NormalS16Morph, &VertexDecoderJitCache::Jit_NormalS16Morph},
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{&VertexDecoder::Step_NormalFloatMorph, &VertexDecoderJitCache::Jit_NormalFloatMorph},
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{&VertexDecoder::Step_PosS8Morph, &VertexDecoderJitCache::Jit_PosS8Morph},
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{&VertexDecoder::Step_PosS16Morph, &VertexDecoderJitCache::Jit_PosS16Morph},
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{&VertexDecoder::Step_PosFloatMorph, &VertexDecoderJitCache::Jit_PosFloatMorph},
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{&VertexDecoder::Step_Color8888Morph, &VertexDecoderJitCache::Jit_Color8888Morph},
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{&VertexDecoder::Step_Color4444Morph, &VertexDecoderJitCache::Jit_Color4444Morph},
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{&VertexDecoder::Step_Color565Morph, &VertexDecoderJitCache::Jit_Color565Morph},
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{&VertexDecoder::Step_Color5551Morph, &VertexDecoderJitCache::Jit_Color5551Morph},
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*/
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};
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JittedVertexDecoder VertexDecoderJitCache::Compile(const VertexDecoder &dec) {
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dec_ = &dec;
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const u32 ALL_CALLEE_SAVED = 0x7FF80000;
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BitSet32 regs_to_save(ALL_CALLEE_SAVED);
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const u8 *start = AlignCode16();
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// TODO: Also push D8-D15, the fp registers we need to save.
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bool prescaleStep = false;
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bool skinning = false;
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// Look for prescaled texcoord steps
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for (int i = 0; i < dec.numSteps_; i++) {
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if (dec.steps_[i] == &VertexDecoder::Step_TcU8Prescale ||
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dec.steps_[i] == &VertexDecoder::Step_TcU16Prescale ||
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dec.steps_[i] == &VertexDecoder::Step_TcFloatPrescale) {
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prescaleStep = true;
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}
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if (dec.steps_[i] == &VertexDecoder::Step_WeightsU8Skin ||
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dec.steps_[i] == &VertexDecoder::Step_WeightsU16Skin ||
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dec.steps_[i] == &VertexDecoder::Step_WeightsFloatSkin) {
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skinning = true;
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}
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}
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ABI_PushRegisters(regs_to_save);
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// Keep the scale/offset in a few fp registers if we need it.
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if (prescaleStep) {
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MOVP2R(X3, &gstate_c.uv);
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if (cpu_info.bNEON) {
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fp.LDR(64, INDEX_UNSIGNED, neonUVScaleReg, X3, 0);
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fp.LDR(64, INDEX_UNSIGNED, neonUVOffsetReg, X3, 8);
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if ((dec.VertexType() & GE_VTYPE_TC_MASK) == GE_VTYPE_TC_8BIT) {
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fp.MOVI2FDUP(neonScratchReg, by128, scratchReg);
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fp.FMUL(32, neonUVScaleReg, neonUVScaleReg, neonScratchReg);
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} else if ((dec.VertexType() & GE_VTYPE_TC_MASK) == GE_VTYPE_TC_16BIT) {
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fp.MOVI2FDUP(neonScratchReg, by32768, scratchReg);
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fp.FMUL(32, neonUVScaleReg, neonUVScaleReg, neonScratchReg);
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}
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}
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}
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if (dec.weighttype && g_Config.bSoftwareSkinning && dec.morphcount == 1) {
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WARN_LOG(HLE, "vtxdec-arm64 does not support sw skinning");
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SetCodePtr(const_cast<u8 *>(start));
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return NULL;
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}
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// Add code to convert matrices to 4x4.
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// Later we might want to do this when the matrices are loaded instead.
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int boneCount = 0;
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if (dec.weighttype && g_Config.bSoftwareSkinning && dec.morphcount == 1) {
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// Copying from R3 to R4
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MOVP2R(X3, gstate.boneMatrix);
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MOVP2R(X4, bones);
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MOVP2R(X5, boneMask);
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fp.LDR(128, INDEX_UNSIGNED, Q3, X5, 0);
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for (int i = 0; i < 8; i++) {
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fp.LDR(128, INDEX_UNSIGNED, Q4, X3, 0); // Load 128 bits even though we just want 96
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fp.LDR(128, INDEX_UNSIGNED, Q5, X3, 12);
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fp.LDR(128, INDEX_UNSIGNED, Q6, X3, 24);
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fp.LDR(128, INDEX_UNSIGNED, Q7, X3, 36);
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fp.FMUL(32, Q4, Q4, Q3);
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fp.FMUL(32, Q5, Q5, Q3);
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fp.FMUL(32, Q6, Q6, Q6);
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fp.FMUL(32, Q7, Q7, Q7);
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// First four matrices are in registers.
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if (i < 4) {
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fp.FMOV((ARM64Reg)(Q16 + i * 4), Q4);
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fp.FMOV((ARM64Reg)(Q17 + i * 4), Q5);
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fp.FMOV((ARM64Reg)(Q18 + i * 4), Q6);
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fp.FMOV((ARM64Reg)(Q19 + i * 4), Q7);
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ADDI2R(X4, X4, 16 * 4);
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} else {
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fp.STR(128, INDEX_UNSIGNED, Q4, X4, 0);
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fp.STR(128, INDEX_UNSIGNED, Q5, X4, 16);
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fp.STR(128, INDEX_UNSIGNED, Q6, X4, 32);
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fp.STR(128, INDEX_UNSIGNED, Q7, X4, 48);
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ADDI2R(X4, X4, 16 * 4);
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}
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}
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}
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if (dec.col) {
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// Or LDB and skip the conditional? This is probably cheaper.
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MOVI2R(fullAlphaReg, 0xFF);
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}
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const u8 *loopStart = GetCodePtr();
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for (int i = 0; i < dec.numSteps_; i++) {
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if (!CompileStep(dec, i)) {
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// Reset the code ptr (effectively undoing what we generated) and return zero to indicate that we failed.
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SetCodePtr(const_cast<u8 *>(start));
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char temp[1024] = {0};
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dec.ToString(temp);
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WARN_LOG(HLE, "Could not compile vertex decoder, failed at step %d: %s", i, temp);
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return 0;
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}
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}
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ADDI2R(srcReg, srcReg, dec.VertexSize(), scratchReg);
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ADDI2R(dstReg, dstReg, dec.decFmt.stride, scratchReg);
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SUBS(counterReg, counterReg, 1);
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B(CC_NEQ, loopStart);
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if (dec.col) {
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MOVP2R(tempRegPtr, &gstate_c.vertexFullAlpha);
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CMP(fullAlphaReg, 0);
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FixupBranch skip = B(CC_NEQ);
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STRB(INDEX_UNSIGNED, fullAlphaReg, tempRegPtr, 0);
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SetJumpTarget(skip);
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}
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ABI_PopRegisters(regs_to_save);
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RET();
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FlushIcache();
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char temp[1024] = { 0 };
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dec.ToString(temp);
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ILOG("=== %s (%d bytes) ===", temp, (int)(GetCodePtr() - start));
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std::vector<std::string> lines = DisassembleArm64(start, GetCodePtr() - start);
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for (auto line : lines) {
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ILOG("%s", line.c_str());
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}
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ILOG("==========", temp);
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return (JittedVertexDecoder)start;
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}
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bool VertexDecoderJitCache::CompileStep(const VertexDecoder &dec, int step) {
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// See if we find a matching JIT function
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for (size_t i = 0; i < ARRAY_SIZE(jitLookup); i++) {
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if (dec.steps_[step] == jitLookup[i].func) {
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((*this).*jitLookup[i].jitFunc)();
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return true;
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}
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}
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return false;
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}
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void VertexDecoderJitCache::Jit_ApplyWeights() {
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// We construct a matrix in Q4-Q7
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// We can use Q1 as temp.
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if (dec_->nweights >= 2) {
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MOVP2R(scratchReg, bones + 16 * 2);
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}
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for (int i = 0; i < dec_->nweights; i++) {
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switch (i) {
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case 0:
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fp.FMUL(32, Q4, Q16, neonWeightRegsQ[0], 0);
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fp.FMUL(32, Q5, Q17, neonWeightRegsQ[0], 0);
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fp.FMUL(32, Q6, Q18, neonWeightRegsQ[0], 0);
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fp.FMUL(32, Q7, Q19, neonWeightRegsQ[0], 0);
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break;
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case 1:
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fp.FMLA(32, Q4, Q20, neonWeightRegsQ[0], 1);
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fp.FMLA(32, Q5, Q21, neonWeightRegsQ[0], 1);
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fp.FMLA(32, Q6, Q22, neonWeightRegsQ[0], 1);
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fp.FMLA(32, Q7, Q23, neonWeightRegsQ[0], 1);
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break;
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case 2:
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fp.FMLA(32, Q4, Q24, neonWeightRegsQ[0], 1);
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fp.FMLA(32, Q5, Q25, neonWeightRegsQ[0], 1);
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fp.FMLA(32, Q6, Q26, neonWeightRegsQ[0], 1);
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fp.FMLA(32, Q7, Q27, neonWeightRegsQ[0], 1);
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break;
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case 3:
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fp.FMLA(32, Q4, Q28, neonWeightRegsQ[0], 1);
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fp.FMLA(32, Q5, Q29, neonWeightRegsQ[0], 1);
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fp.FMLA(32, Q6, Q30, neonWeightRegsQ[0], 1);
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fp.FMLA(32, Q7, Q31, neonWeightRegsQ[0], 1);
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break;
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default:
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// Matrices 2+ need to be loaded from memory.
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// Wonder if we can free up one more register so we could get some parallelism.
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// Actually Q3 is free if there are fewer than 5 weights...
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fp.LDP(INDEX_SIGNED, Q8, Q9, scratchReg, 0);
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fp.LDP(INDEX_SIGNED, Q10, Q11, scratchReg, 2 * 16);
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fp.FMLA(32, Q4, Q8, neonWeightRegsQ[i >> 2], i & 3);
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fp.FMLA(32, Q5, Q9, neonWeightRegsQ[i >> 2], i & 3);
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fp.FMLA(32, Q6, Q10, neonWeightRegsQ[i >> 2], i & 3);
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fp.FMLA(32, Q7, Q11, neonWeightRegsQ[i >> 2], i & 3);
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ADDI2R(scratchReg, scratchReg, 4 * 16);
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break;
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}
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}
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}
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void VertexDecoderJitCache::Jit_WeightsU8() {
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// Basic implementation - a byte at a time. TODO: Optimize
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int j;
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for (j = 0; j < dec_->nweights; j++) {
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LDRB(INDEX_UNSIGNED, tempReg1, srcReg, dec_->weightoff + j);
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STRB(INDEX_UNSIGNED, tempReg1, dstReg, dec_->decFmt.w0off + j);
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}
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if (j & 3) {
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// Create a zero register. Might want to make a fixed one.
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EOR(scratchReg, scratchReg, scratchReg);
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}
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while (j & 3) {
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STRB(INDEX_UNSIGNED, scratchReg, dstReg, dec_->decFmt.w0off + j);
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j++;
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}
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}
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void VertexDecoderJitCache::Jit_WeightsU16() {
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// Basic implementation - a short at a time. TODO: Optimize
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int j;
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for (j = 0; j < dec_->nweights; j++) {
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LDRH(INDEX_UNSIGNED, tempReg1, srcReg, dec_->weightoff + j * 2);
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STRH(INDEX_UNSIGNED, tempReg1, dstReg, dec_->decFmt.w0off + j * 2);
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}
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if (j & 3) {
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// Create a zero register. Might want to make a fixed one.
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EOR(scratchReg, scratchReg, scratchReg);
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}
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while (j & 3) {
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STRH(INDEX_UNSIGNED, scratchReg, dstReg, dec_->decFmt.w0off + j * 2);
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j++;
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}
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}
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void VertexDecoderJitCache::Jit_WeightsFloat() {
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int j;
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for (j = 0; j < dec_->nweights; j++) {
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LDR(INDEX_UNSIGNED, tempReg1, srcReg, dec_->weightoff + j * 4);
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STR(INDEX_UNSIGNED, tempReg1, dstReg, dec_->decFmt.w0off + j * 4);
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}
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if (j & 3) {
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EOR(tempReg1, tempReg1, tempReg1);
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}
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while (j & 3) { // Zero additional weights rounding up to 4.
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STR(INDEX_UNSIGNED, tempReg1, dstReg, dec_->decFmt.w0off + j * 4);
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j++;
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}
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}
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void VertexDecoderJitCache::Jit_WeightsU8Skin() {
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// Weight is first so srcReg is correct.
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switch (dec_->nweights) {
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case 1: fp.LDR(8, INDEX_UNSIGNED, neonScratchReg, srcReg, 0); break;
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case 2: fp.LDR(16, INDEX_UNSIGNED, neonScratchReg, srcReg, 0); break;
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default:
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// For 3, we over read, for over 4, we read more later.
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fp.LDR(32, INDEX_UNSIGNED, neonScratchReg, srcReg, 0);
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break;
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}
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// TODO: Get rid of this constant, use fixed point conversion
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fp.MOVI2FDUP(Q3, by128, X0);
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fp.UXTL(8, neonScratchRegQ, neonScratchReg);
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fp.UXTL(16, neonScratchRegQ, neonScratchReg);
|
|
fp.UCVTF(neonScratchRegQ, neonScratchRegQ);
|
|
fp.FMUL(32, neonWeightRegsQ[0], neonScratchRegQ, Q3);
|
|
|
|
if (dec_->nweights > 4) {
|
|
switch (dec_->nweights) {
|
|
case 5: fp.LDR(8, INDEX_UNSIGNED, neonScratchReg, srcReg, 4); break;
|
|
case 6: fp.LDR(16, INDEX_UNSIGNED, neonScratchReg, srcReg, 4); break;
|
|
case 7:
|
|
case 8:
|
|
fp.LDR(32, INDEX_UNSIGNED, neonScratchReg, srcReg, 4);
|
|
break;
|
|
}
|
|
fp.UXTL(8, neonScratchRegQ, neonScratchReg);
|
|
fp.UXTL(16, neonScratchRegQ, neonScratchReg);
|
|
fp.UCVTF(neonScratchRegQ, neonScratchRegQ);
|
|
fp.FMUL(32, neonWeightRegsQ[1], neonScratchRegQ, Q3);
|
|
}
|
|
Jit_ApplyWeights();
|
|
}
|
|
|
|
void VertexDecoderJitCache::Jit_WeightsU16Skin() {
|
|
switch (dec_->nweights) {
|
|
case 1: fp.LDR(16, INDEX_UNSIGNED, neonScratchReg, srcReg, 0); break;
|
|
case 2: fp.LDR(32, INDEX_UNSIGNED, neonScratchReg, srcReg, 0); break;
|
|
default:
|
|
// For 3, we over read, for over 4, we read more later.
|
|
fp.LDR(64, INDEX_UNSIGNED, neonScratchReg, srcReg, 0);
|
|
break;
|
|
}
|
|
fp.MOVI2FDUP(Q3, by32768, X0);
|
|
fp.UXTL(16, neonScratchRegQ, neonScratchReg);
|
|
fp.UCVTF(neonScratchRegQ, neonScratchRegQ);
|
|
fp.FMUL(32, neonWeightRegsQ[0], neonScratchRegQ, Q3);
|
|
|
|
if (dec_->nweights > 4) {
|
|
switch (dec_->nweights) {
|
|
case 5: fp.LDR(16, INDEX_UNSIGNED, neonScratchReg, srcReg, 8); break;
|
|
case 6: fp.LDR(32, INDEX_UNSIGNED, neonScratchReg, srcReg, 8); break;
|
|
case 7:
|
|
case 8:
|
|
fp.LDR(64, INDEX_UNSIGNED, neonScratchReg, srcReg, 8);
|
|
break;
|
|
}
|
|
fp.UXTL(16, neonScratchRegQ, neonScratchReg);
|
|
fp.UCVTF(neonScratchRegQ, neonScratchRegQ);
|
|
fp.FMUL(32, neonWeightRegsQ[1], neonScratchRegQ, Q3);
|
|
}
|
|
Jit_ApplyWeights();
|
|
}
|
|
|
|
void VertexDecoderJitCache::Jit_WeightsFloatSkin() {
|
|
switch (dec_->nweights) {
|
|
case 1:
|
|
fp.LDR(32, INDEX_UNSIGNED, neonWeightRegsQ[0], srcReg, 0);
|
|
break;
|
|
case 2:
|
|
fp.LDR(64, INDEX_UNSIGNED, neonWeightRegsQ[0], srcReg, 0);
|
|
break;
|
|
case 3:
|
|
case 4:
|
|
fp.LDR(128, INDEX_UNSIGNED, neonWeightRegsQ[0], srcReg, 0);
|
|
break;
|
|
|
|
case 5:
|
|
fp.LDR(128, INDEX_UNSIGNED, neonWeightRegsQ[0], srcReg, 0);
|
|
fp.LDR(32, INDEX_UNSIGNED, neonWeightRegsQ[1], srcReg, 16);
|
|
break;
|
|
case 6:
|
|
fp.LDR(128, INDEX_UNSIGNED, neonWeightRegsQ[0], srcReg, 0);
|
|
fp.LDR(64, INDEX_UNSIGNED, neonWeightRegsQ[1], srcReg, 16);
|
|
break;
|
|
case 7:
|
|
case 8:
|
|
fp.LDR(128, INDEX_UNSIGNED, neonWeightRegsQ[0], srcReg, 0);
|
|
fp.LDR(128, INDEX_UNSIGNED, neonWeightRegsQ[1], srcReg, 16);
|
|
break;
|
|
}
|
|
Jit_ApplyWeights();
|
|
}
|
|
|
|
void VertexDecoderJitCache::Jit_Color8888() {
|
|
LDR(INDEX_UNSIGNED, tempReg1, srcReg, dec_->coloff);
|
|
// TODO: Set flags to determine if alpha != 0xFF.
|
|
// ANDSI2R(tempReg2, tempReg1, 0xFF000000);
|
|
STR(INDEX_UNSIGNED, tempReg1, dstReg, dec_->decFmt.c0off);
|
|
// FixupBranch skip = B(CC_NZ);
|
|
MOVI2R(fullAlphaReg, 0);
|
|
// SetJumpTarget(skip);
|
|
}
|
|
|
|
void VertexDecoderJitCache::Jit_TcU8() {
|
|
LDRB(INDEX_UNSIGNED, tempReg1, srcReg, dec_->tcoff);
|
|
LDRB(INDEX_UNSIGNED, tempReg2, srcReg, dec_->tcoff + 1);
|
|
ORR(tempReg1, tempReg1, tempReg2, ArithOption(tempReg2, ST_LSL, 8));
|
|
STR(INDEX_UNSIGNED, tempReg1, dstReg, dec_->decFmt.uvoff);
|
|
}
|
|
|
|
void VertexDecoderJitCache::Jit_TcU16() {
|
|
LDRH(INDEX_UNSIGNED, tempReg1, srcReg, dec_->tcoff);
|
|
LDRH(INDEX_UNSIGNED, tempReg2, srcReg, dec_->tcoff + 2);
|
|
ORR(tempReg1, tempReg1, tempReg2, ArithOption(tempReg2, ST_LSL, 16));
|
|
STR(INDEX_UNSIGNED, tempReg1, dstReg, dec_->decFmt.uvoff);
|
|
}
|
|
|
|
void VertexDecoderJitCache::Jit_TcU16Through() {
|
|
LDRH(INDEX_UNSIGNED, tempReg1, srcReg, dec_->tcoff);
|
|
LDRH(INDEX_UNSIGNED, tempReg2, srcReg, dec_->tcoff + 2);
|
|
ORR(tempReg1, tempReg1, tempReg2, ArithOption(tempReg2, ST_LSL, 16));
|
|
STR(INDEX_UNSIGNED, tempReg1, dstReg, dec_->decFmt.uvoff);
|
|
}
|
|
|
|
void VertexDecoderJitCache::Jit_TcFloatThrough() {
|
|
LDR(INDEX_UNSIGNED, tempReg1, srcReg, dec_->tcoff);
|
|
LDR(INDEX_UNSIGNED, tempReg2, srcReg, dec_->tcoff + 4);
|
|
STR(INDEX_UNSIGNED, tempReg1, dstReg, dec_->decFmt.uvoff);
|
|
STR(INDEX_UNSIGNED, tempReg2, dstReg, dec_->decFmt.uvoff + 4);
|
|
}
|
|
|
|
void VertexDecoderJitCache::Jit_TcU16Double() {
|
|
LDRH(INDEX_UNSIGNED, tempReg1, srcReg, dec_->tcoff);
|
|
LDRH(INDEX_UNSIGNED, tempReg2, srcReg, dec_->tcoff + 2);
|
|
LSL(tempReg1, tempReg1, 1);
|
|
ORR(tempReg1, tempReg1, tempReg2, ArithOption(tempReg2, ST_LSL, 17));
|
|
STR(INDEX_UNSIGNED, tempReg1, dstReg, dec_->decFmt.uvoff);
|
|
}
|
|
|
|
void VertexDecoderJitCache::Jit_TcU16ThroughDouble() {
|
|
LDRH(INDEX_UNSIGNED, tempReg1, srcReg, dec_->tcoff);
|
|
LDRH(INDEX_UNSIGNED, tempReg2, srcReg, dec_->tcoff + 2);
|
|
LSL(tempReg1, tempReg1, 1);
|
|
ORR(tempReg1, tempReg1, tempReg2, ArithOption(tempReg2, ST_LSL, 17));
|
|
STR(INDEX_UNSIGNED, tempReg1, dstReg, dec_->decFmt.uvoff);
|
|
}
|
|
|
|
void VertexDecoderJitCache::Jit_TcFloat() {
|
|
LDR(INDEX_UNSIGNED, tempReg1, srcReg, dec_->tcoff);
|
|
LDR(INDEX_UNSIGNED, tempReg2, srcReg, dec_->tcoff + 4);
|
|
STR(INDEX_UNSIGNED, tempReg1, dstReg, dec_->decFmt.uvoff);
|
|
STR(INDEX_UNSIGNED, tempReg2, dstReg, dec_->decFmt.uvoff + 4);
|
|
}
|
|
|
|
void VertexDecoderJitCache::Jit_TcU8Prescale() {
|
|
fp.LDR(16, INDEX_UNSIGNED, neonScratchReg, srcReg, dec_->tcoff);
|
|
fp.UXTL(8, neonScratchRegQ, neonScratchReg); // Widen to 16-bit
|
|
fp.UXTL(16, neonScratchRegQ, neonScratchReg); // Widen to 32-bit
|
|
fp.SCVTF(32, neonScratchReg, neonScratchReg);
|
|
fp.FMUL(32, neonScratchReg, neonScratchReg, neonUVScaleReg); // TODO: FMLA
|
|
fp.FADD(32, neonScratchReg, neonScratchReg, neonUVOffsetReg);
|
|
fp.STR(64, INDEX_UNSIGNED, neonScratchReg, dstReg, dec_->decFmt.uvoff);
|
|
}
|
|
|
|
void VertexDecoderJitCache::Jit_TcU16Prescale() {
|
|
fp.LDR(32, INDEX_UNSIGNED, neonScratchReg, srcReg, dec_->tcoff);
|
|
fp.UXTL(16, neonScratchRegQ, neonScratchReg); // Widen to 32-bit
|
|
fp.SCVTF(32, neonScratchReg, neonScratchReg);
|
|
fp.FMUL(32, neonScratchReg, neonScratchReg, neonUVScaleReg); // TODO: FMLA
|
|
fp.FADD(32, neonScratchReg, neonScratchReg, neonUVOffsetReg);
|
|
fp.STR(64, INDEX_UNSIGNED, neonScratchReg, dstReg, dec_->decFmt.uvoff);
|
|
}
|
|
|
|
void VertexDecoderJitCache::Jit_TcFloatPrescale() {
|
|
fp.LDR(64, INDEX_UNSIGNED, neonScratchReg, srcReg, dec_->tcoff);
|
|
fp.FMUL(32, neonScratchReg, neonScratchReg, neonUVScaleReg); // TODO: FMLA
|
|
fp.FADD(32, neonScratchReg, neonScratchReg, neonUVOffsetReg);
|
|
fp.STR(64, INDEX_UNSIGNED, neonScratchReg, dstReg, dec_->decFmt.uvoff);
|
|
}
|
|
|
|
void VertexDecoderJitCache::Jit_PosS8() {
|
|
Jit_AnyS8ToFloat(dec_->posoff);
|
|
STR(INDEX_UNSIGNED, src[0], dstReg, dec_->decFmt.posoff);
|
|
STR(INDEX_UNSIGNED, src[1], dstReg, dec_->decFmt.posoff + 4);
|
|
STR(INDEX_UNSIGNED, src[2], dstReg, dec_->decFmt.posoff + 8);
|
|
}
|
|
|
|
void VertexDecoderJitCache::Jit_PosS16() {
|
|
Jit_AnyS16ToFloat(dec_->posoff);
|
|
STR(INDEX_UNSIGNED, src[0], dstReg, dec_->decFmt.posoff);
|
|
STR(INDEX_UNSIGNED, src[1], dstReg, dec_->decFmt.posoff + 4);
|
|
STR(INDEX_UNSIGNED, src[2], dstReg, dec_->decFmt.posoff + 8);
|
|
}
|
|
|
|
// Just copy 12 bytes.
|
|
void VertexDecoderJitCache::Jit_PosFloat() {
|
|
LDR(INDEX_UNSIGNED, tempReg1, srcReg, dec_->posoff);
|
|
LDR(INDEX_UNSIGNED, tempReg2, srcReg, dec_->posoff + 4);
|
|
LDR(INDEX_UNSIGNED, tempReg3, srcReg, dec_->posoff + 8);
|
|
STR(INDEX_UNSIGNED, tempReg1, dstReg, dec_->decFmt.posoff);
|
|
STR(INDEX_UNSIGNED, tempReg2, dstReg, dec_->decFmt.posoff + 4);
|
|
STR(INDEX_UNSIGNED, tempReg3, dstReg, dec_->decFmt.posoff + 8);
|
|
}
|
|
|
|
void VertexDecoderJitCache::Jit_PosS16Through() {
|
|
LDRSH(INDEX_UNSIGNED, tempReg1, srcReg, dec_->posoff);
|
|
LDRSH(INDEX_UNSIGNED, tempReg2, srcReg, dec_->posoff + 2);
|
|
LDRH(INDEX_UNSIGNED, tempReg3, srcReg, dec_->posoff + 4);
|
|
fp.SCVTF(fpScratchReg, tempReg1);
|
|
fp.SCVTF(fpScratchReg2, tempReg2);
|
|
fp.SCVTF(fpScratchReg3, tempReg3);
|
|
STR(INDEX_UNSIGNED, fpScratchReg, dstReg, dec_->decFmt.posoff);
|
|
STR(INDEX_UNSIGNED, fpScratchReg2, dstReg, dec_->decFmt.posoff + 4);
|
|
STR(INDEX_UNSIGNED, fpScratchReg3, dstReg, dec_->decFmt.posoff + 8);
|
|
}
|
|
|
|
void VertexDecoderJitCache::Jit_NormalS8() {
|
|
LDRB(INDEX_UNSIGNED, tempReg1, srcReg, dec_->nrmoff);
|
|
LDRB(INDEX_UNSIGNED, tempReg2, srcReg, dec_->nrmoff + 1);
|
|
LDRB(INDEX_UNSIGNED, tempReg3, srcReg, dec_->nrmoff + 2);
|
|
ORR(tempReg1, tempReg1, tempReg2, ArithOption(tempReg2, ST_LSL, 8));
|
|
ORR(tempReg1, tempReg1, tempReg3, ArithOption(tempReg3, ST_LSL, 16));
|
|
STR(INDEX_UNSIGNED, tempReg1, dstReg, dec_->decFmt.nrmoff);
|
|
}
|
|
|
|
// Copy 6 bytes and then 2 zeroes.
|
|
void VertexDecoderJitCache::Jit_NormalS16() {
|
|
LDRH(INDEX_UNSIGNED, tempReg1, srcReg, dec_->nrmoff);
|
|
LDRH(INDEX_UNSIGNED, tempReg2, srcReg, dec_->nrmoff + 2);
|
|
LDRH(INDEX_UNSIGNED, tempReg3, srcReg, dec_->nrmoff + 4);
|
|
ORR(tempReg1, tempReg1, tempReg2, ArithOption(tempReg2, ST_LSL, 16));
|
|
STR(INDEX_UNSIGNED, tempReg1, dstReg, dec_->decFmt.nrmoff);
|
|
STR(INDEX_UNSIGNED, tempReg3, dstReg, dec_->decFmt.nrmoff + 4);
|
|
}
|
|
|
|
void VertexDecoderJitCache::Jit_NormalFloat() {
|
|
LDR(INDEX_UNSIGNED, tempReg1, srcReg, dec_->nrmoff);
|
|
LDR(INDEX_UNSIGNED, tempReg2, srcReg, dec_->nrmoff + 4);
|
|
LDR(INDEX_UNSIGNED, tempReg3, srcReg, dec_->nrmoff + 8);
|
|
STR(INDEX_UNSIGNED, tempReg1, dstReg, dec_->decFmt.nrmoff);
|
|
STR(INDEX_UNSIGNED, tempReg2, dstReg, dec_->decFmt.nrmoff + 4);
|
|
STR(INDEX_UNSIGNED, tempReg3, dstReg, dec_->decFmt.nrmoff + 8);
|
|
}
|
|
|
|
void VertexDecoderJitCache::Jit_NormalS8Skin() {
|
|
Jit_AnyS8ToFloat(dec_->nrmoff);
|
|
Jit_WriteMatrixMul(dec_->decFmt.nrmoff, false);
|
|
}
|
|
|
|
void VertexDecoderJitCache::Jit_NormalS16Skin() {
|
|
Jit_AnyS16ToFloat(dec_->nrmoff);
|
|
Jit_WriteMatrixMul(dec_->decFmt.nrmoff, false);
|
|
}
|
|
|
|
void VertexDecoderJitCache::Jit_NormalFloatSkin() {
|
|
fp.LDR(128, INDEX_UNSIGNED, srcNEON, srcReg, dec_->nrmoff);
|
|
Jit_WriteMatrixMul(dec_->decFmt.nrmoff, false);
|
|
}
|
|
|
|
void VertexDecoderJitCache::Jit_PosS8Skin() {
|
|
Jit_AnyS8ToFloat(dec_->posoff);
|
|
Jit_WriteMatrixMul(dec_->decFmt.posoff, true);
|
|
}
|
|
|
|
void VertexDecoderJitCache::Jit_PosS16Skin() {
|
|
Jit_AnyS16ToFloat(dec_->posoff);
|
|
Jit_WriteMatrixMul(dec_->decFmt.posoff, true);
|
|
}
|
|
|
|
void VertexDecoderJitCache::Jit_PosFloatSkin() {
|
|
fp.LDR(128, INDEX_UNSIGNED, srcNEON, srcReg, dec_->posoff);
|
|
Jit_WriteMatrixMul(dec_->decFmt.posoff, true);
|
|
}
|
|
|
|
void VertexDecoderJitCache::Jit_AnyS8ToFloat(int srcoff) {
|
|
// TODO: NEONize. In that case we'll leave all three floats in one register instead, so callers must change too.
|
|
LDRSB(INDEX_UNSIGNED, tempReg1, srcReg, srcoff);
|
|
LDRSB(INDEX_UNSIGNED, tempReg2, srcReg, srcoff + 1);
|
|
LDRSB(INDEX_UNSIGNED, tempReg3, srcReg, srcoff + 2);
|
|
fp.SCVTF(src[0], tempReg1, 7);
|
|
fp.SCVTF(src[1], tempReg2, 7);
|
|
fp.SCVTF(src[2], tempReg3, 7);
|
|
}
|
|
|
|
void VertexDecoderJitCache::Jit_AnyS16ToFloat(int srcoff) {
|
|
LDRSH(INDEX_UNSIGNED, tempReg1, srcReg, srcoff);
|
|
LDRSH(INDEX_UNSIGNED, tempReg2, srcReg, srcoff + 2);
|
|
LDRSH(INDEX_UNSIGNED, tempReg3, srcReg, srcoff + 4);
|
|
fp.SCVTF(src[0], tempReg1, 15);
|
|
fp.SCVTF(src[1], tempReg2, 15);
|
|
fp.SCVTF(src[2], tempReg3, 15);
|
|
}
|
|
|
|
void VertexDecoderJitCache::Jit_WriteMatrixMul(int outOff, bool pos) {
|
|
// Multiply with the matrix sitting in Q4-Q7.
|
|
fp.FMUL(32, accNEON, Q4, srcNEON, 0);
|
|
fp.FMLA(32, accNEON, Q5, srcNEON, 1);
|
|
fp.FMLA(32, accNEON, Q6, srcNEON, 2);
|
|
if (pos) {
|
|
fp.FADD(32, accNEON, accNEON, Q7);
|
|
}
|
|
fp.STR(128, INDEX_UNSIGNED, accNEON, dstReg, outOff);
|
|
}
|