667 lines
18 KiB
C++
667 lines
18 KiB
C++
// Copyright (c) 2012- PPSSPP Project.
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, version 2.0 or later versions.
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License 2.0 for more details.
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// A copy of the GPL 2.0 should have been included with the program.
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// If not, see http://www.gnu.org/licenses/
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// Official git repository and contact information can be found at
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// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
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#include "Core/Reporting.h"
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#include "Core/Config.h"
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#include "Core/HLE/HLE.h"
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#include "Core/HLE/HLETables.h"
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#include "Core/Host.h"
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#include "Core/MIPS/MIPS.h"
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#include "Core/MIPS/MIPSCodeUtils.h"
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#include "Core/MIPS/MIPSAnalyst.h"
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#include "Core/MIPS/MIPSTables.h"
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#include "Core/MIPS/x86/Jit.h"
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#include "Core/MIPS/x86/RegCache.h"
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#include "Core/MIPS/JitCommon/JitBlockCache.h"
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#define _RS MIPS_GET_RS(op)
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#define _RT MIPS_GET_RT(op)
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#define _RD MIPS_GET_RD(op)
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#define _FS MIPS_GET_FS(op)
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#define _FT MIPS_GET_FT(op)
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#define _FD MIPS_GET_FD(op)
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#define _SA MIPS_GET_SA(op)
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#define _POS ((op>> 6) & 0x1F)
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#define _SIZE ((op>>11) & 0x1F)
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#define _IMM16 (signed short)(op & 0xFFFF)
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#define _IMM26 (op & 0x03FFFFFF)
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#define LOOPOPTIMIZATION 0
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using namespace MIPSAnalyst;
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// NOTE: Can't use CONDITIONAL_DISABLE in this file, branches are so special
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// that they cannot be interpreted in the context of the Jit.
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// But we can at least log and compare.
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// #define DO_CONDITIONAL_LOG 1
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#define DO_CONDITIONAL_LOG 0
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// We can also disable nice delay slots.
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// #define CONDITIONAL_NICE_DELAYSLOT delaySlotIsNice = false;
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#define CONDITIONAL_NICE_DELAYSLOT ;
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#if DO_CONDITIONAL_LOG
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#define CONDITIONAL_LOG BranchLog(op);
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#define CONDITIONAL_LOG_EXIT(addr) BranchLogExit(op, addr, false);
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#define CONDITIONAL_LOG_EXIT_EAX() BranchLogExit(op, 0, true);
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#else
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#define CONDITIONAL_LOG ;
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#define CONDITIONAL_LOG_EXIT(addr) ;
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#define CONDITIONAL_LOG_EXIT_EAX() ;
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#endif
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namespace MIPSComp
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{
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static u32 intBranchExit;
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static u32 jitBranchExit;
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static void JitBranchLog(MIPSOpcode op, u32 pc)
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{
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currentMIPS->pc = pc;
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currentMIPS->inDelaySlot = false;
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MIPSInterpretFunc func = MIPSGetInterpretFunc(op);
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MIPSInfo info = MIPSGetInfo(op);
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func(op);
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// Branch taken, use nextPC.
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if (currentMIPS->inDelaySlot)
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intBranchExit = currentMIPS->nextPC;
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else
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{
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// Branch not taken, likely delay slot skipped.
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if (info & LIKELY)
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intBranchExit = currentMIPS->pc;
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// Branch not taken, so increment over delay slot.
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else
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intBranchExit = currentMIPS->pc + 4;
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}
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currentMIPS->pc = pc;
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currentMIPS->inDelaySlot = false;
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}
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static void JitBranchLogMismatch(MIPSOpcode op, u32 pc)
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{
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char temp[256];
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MIPSDisAsm(op, pc, temp, true);
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ERROR_LOG(JIT, "Bad jump: %s - int:%08x jit:%08x", temp, intBranchExit, jitBranchExit);
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host->SetDebugMode(true);
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}
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void Jit::BranchLog(MIPSOpcode op)
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{
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FlushAll();
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ABI_CallFunctionCC(thunks.ProtectFunction((void *) &JitBranchLog, 2), op.encoding, js.compilerPC);
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}
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void Jit::BranchLogExit(MIPSOpcode op, u32 dest, bool useEAX)
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{
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OpArg destArg = useEAX ? R(EAX) : Imm32(dest);
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CMP(32, M((void *) &intBranchExit), destArg);
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FixupBranch skip = J_CC(CC_E);
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MOV(32, M((void *) &jitBranchExit), destArg);
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ABI_CallFunctionCC(thunks.ProtectFunction((void *) &JitBranchLogMismatch, 2), op.encoding, js.compilerPC);
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// Restore EAX, we probably ruined it.
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if (useEAX)
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MOV(32, R(EAX), M((void *) &jitBranchExit));
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SetJumpTarget(skip);
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}
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void Jit::BranchRSRTComp(MIPSOpcode op, Gen::CCFlags cc, bool likely)
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{
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CONDITIONAL_LOG;
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if (js.inDelaySlot) {
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ERROR_LOG_REPORT(JIT, "Branch in RSRTComp delay slot at %08x in block starting at %08x", js.compilerPC, js.blockStart);
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return;
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}
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int offset = _IMM16 << 2;
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MIPSGPReg rt = _RT;
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MIPSGPReg rs = _RS;
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u32 targetAddr = js.compilerPC + offset + 4;
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MIPSOpcode delaySlotOp = Memory::Read_Instruction(js.compilerPC+4);
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bool delaySlotIsNice = IsDelaySlotNiceReg(op, delaySlotOp, rt, rs);
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CONDITIONAL_NICE_DELAYSLOT;
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if (jo.immBranches && gpr.IsImmediate(rs) && gpr.IsImmediate(rt) && js.numInstructions < jo.continueMaxInstructions)
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{
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// The cc flags are opposites: when NOT to take the branch.
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bool skipBranch;
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s32 rsImm = (s32)gpr.GetImmediate32(rs);
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s32 rtImm = (s32)gpr.GetImmediate32(rt);
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switch (cc)
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{
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case CC_E: skipBranch = rsImm == rtImm; break;
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case CC_NE: skipBranch = rsImm != rtImm; break;
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default: skipBranch = false; _dbg_assert_msg_(JIT, false, "Bad cc flag in BranchRSRTComp().");
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}
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if (skipBranch)
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{
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// Skip the delay slot if likely, otherwise it'll be the next instruction.
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if (likely)
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js.compilerPC += 4;
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return;
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}
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// Branch taken. Always compile the delay slot, and then go to dest.
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CompileDelaySlot(DELAYSLOT_NICE);
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// Account for the increment in the loop.
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js.compilerPC = targetAddr - 4;
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// In case the delay slot was a break or something.
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js.compiling = true;
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return;
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}
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if (!likely && delaySlotIsNice)
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CompileDelaySlot(DELAYSLOT_NICE);
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if (gpr.IsImmediate(rt) && gpr.GetImmediate32(rt) == 0)
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{
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gpr.KillImmediate(rs, true, false);
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CMP(32, gpr.R(rs), Imm32(0));
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}
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else
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{
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gpr.BindToRegister(rs, true, false);
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CMP(32, gpr.R(rs), rt == MIPS_REG_ZERO ? Imm32(0) : gpr.R(rt));
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}
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Gen::FixupBranch ptr;
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RegCacheState state;
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if (!likely)
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{
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if (!delaySlotIsNice)
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CompileDelaySlot(DELAYSLOT_SAFE_FLUSH, state);
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else
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GetStateAndFlushAll(state);
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ptr = J_CC(cc, true);
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}
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else
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{
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GetStateAndFlushAll(state);
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ptr = J_CC(cc, true);
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CompileDelaySlot(DELAYSLOT_FLUSH);
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}
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// Take the branch
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CONDITIONAL_LOG_EXIT(targetAddr);
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WriteExit(targetAddr, js.nextExit++);
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SetJumpTarget(ptr);
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// Not taken
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CONDITIONAL_LOG_EXIT(js.compilerPC + 8);
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if (CanContinueBranch())
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{
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// Account for the delay slot.
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js.compilerPC += 4;
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RestoreState(state);
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// In case the delay slot was a break or something.
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js.compiling = true;
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}
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else
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{
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WriteExit(js.compilerPC + 8, js.nextExit++);
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js.compiling = false;
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}
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}
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void Jit::BranchRSZeroComp(MIPSOpcode op, Gen::CCFlags cc, bool andLink, bool likely)
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{
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CONDITIONAL_LOG;
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if (js.inDelaySlot) {
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ERROR_LOG_REPORT(JIT, "Branch in RSZeroComp delay slot at %08x in block starting at %08x", js.compilerPC, js.blockStart);
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return;
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}
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int offset = _IMM16 << 2;
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MIPSGPReg rs = _RS;
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u32 targetAddr = js.compilerPC + offset + 4;
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MIPSOpcode delaySlotOp = Memory::Read_Instruction(js.compilerPC + 4);
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bool delaySlotIsNice = IsDelaySlotNiceReg(op, delaySlotOp, rs);
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CONDITIONAL_NICE_DELAYSLOT;
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if (jo.immBranches && gpr.IsImmediate(rs) && js.numInstructions < jo.continueMaxInstructions)
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{
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// The cc flags are opposites: when NOT to take the branch.
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bool skipBranch;
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s32 imm = (s32)gpr.GetImmediate32(rs);
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switch (cc)
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{
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case CC_G: skipBranch = imm > 0; break;
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case CC_GE: skipBranch = imm >= 0; break;
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case CC_L: skipBranch = imm < 0; break;
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case CC_LE: skipBranch = imm <= 0; break;
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default: skipBranch = false; _dbg_assert_msg_(JIT, false, "Bad cc flag in BranchRSZeroComp().");
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}
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if (skipBranch)
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{
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// Skip the delay slot if likely, otherwise it'll be the next instruction.
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if (likely)
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js.compilerPC += 4;
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return;
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}
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// Branch taken. Always compile the delay slot, and then go to dest.
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CompileDelaySlot(DELAYSLOT_NICE);
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if (andLink)
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{
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gpr.BindToRegister(MIPS_REG_RA, false, true);
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MOV(32, gpr.R(MIPS_REG_RA), Imm32(js.compilerPC + 8));
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}
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// Account for the increment in the loop.
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js.compilerPC = targetAddr - 4;
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// In case the delay slot was a break or something.
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js.compiling = true;
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return;
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}
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if (!likely && delaySlotIsNice)
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CompileDelaySlot(DELAYSLOT_NICE);
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gpr.BindToRegister(rs, true, false);
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CMP(32, gpr.R(rs), Imm32(0));
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Gen::FixupBranch ptr;
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RegCacheState state;
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if (!likely)
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{
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if (!delaySlotIsNice)
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CompileDelaySlot(DELAYSLOT_SAFE_FLUSH, state);
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else
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GetStateAndFlushAll(state);
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ptr = J_CC(cc, true);
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}
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else
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{
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GetStateAndFlushAll(state);
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ptr = J_CC(cc, true);
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CompileDelaySlot(DELAYSLOT_FLUSH);
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}
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// Take the branch
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if (andLink)
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MOV(32, M(&mips_->r[MIPS_REG_RA]), Imm32(js.compilerPC + 8));
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CONDITIONAL_LOG_EXIT(targetAddr);
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WriteExit(targetAddr, js.nextExit++);
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SetJumpTarget(ptr);
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// Not taken
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CONDITIONAL_LOG_EXIT(js.compilerPC + 8);
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if (CanContinueBranch())
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{
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// Account for the delay slot.
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js.compilerPC += 4;
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RestoreState(state);
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// In case the delay slot was a break or something.
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js.compiling = true;
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}
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else
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{
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WriteExit(js.compilerPC + 8, js.nextExit++);
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js.compiling = false;
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}
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}
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void Jit::Comp_RelBranch(MIPSOpcode op)
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{
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switch (op>>26)
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{
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case 4: BranchRSRTComp(op, CC_NZ, false); break;//beq
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case 5: BranchRSRTComp(op, CC_Z, false); break;//bne
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case 6: BranchRSZeroComp(op, CC_G, false, false); break;//blez
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case 7: BranchRSZeroComp(op, CC_LE, false, false); break;//bgtz
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case 20: BranchRSRTComp(op, CC_NZ, true); break;//beql
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case 21: BranchRSRTComp(op, CC_Z, true); break;//bnel
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case 22: BranchRSZeroComp(op, CC_G, false, true); break;//blezl
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case 23: BranchRSZeroComp(op, CC_LE, false, true); break;//bgtzl
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default:
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_dbg_assert_msg_(CPU,0,"Trying to compile instruction that can't be compiled");
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break;
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}
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}
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void Jit::Comp_RelBranchRI(MIPSOpcode op)
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{
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switch ((op >> 16) & 0x1F)
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{
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case 0: BranchRSZeroComp(op, CC_GE, false, false); break; //if ((s32)R(rs) < 0) DelayBranchTo(addr); else PC += 4; break;//bltz
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case 1: BranchRSZeroComp(op, CC_L, false, false); break; //if ((s32)R(rs) >= 0) DelayBranchTo(addr); else PC += 4; break;//bgez
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case 2: BranchRSZeroComp(op, CC_GE, false, true); break; //if ((s32)R(rs) < 0) DelayBranchTo(addr); else PC += 8; break;//bltzl
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case 3: BranchRSZeroComp(op, CC_L, false, true); break; //if ((s32)R(rs) >= 0) DelayBranchTo(addr); else PC += 8; break;//bgezl
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case 16: BranchRSZeroComp(op, CC_GE, true, false); break; //R(MIPS_REG_RA) = PC + 8; if ((s32)R(rs) < 0) DelayBranchTo(addr); else PC += 4; break;//bltzal
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case 17: BranchRSZeroComp(op, CC_L, true, false); break; //R(MIPS_REG_RA) = PC + 8; if ((s32)R(rs) >= 0) DelayBranchTo(addr); else PC += 4; break;//bgezal
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case 18: BranchRSZeroComp(op, CC_GE, true, true); break; //R(MIPS_REG_RA) = PC + 8; if ((s32)R(rs) < 0) DelayBranchTo(addr); else SkipLikely(); break;//bltzall
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case 19: BranchRSZeroComp(op, CC_L, true, true); break; //R(MIPS_REG_RA) = PC + 8; if ((s32)R(rs) >= 0) DelayBranchTo(addr); else SkipLikely(); break;//bgezall
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default:
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_dbg_assert_msg_(CPU,0,"Trying to compile instruction that can't be compiled");
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break;
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}
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}
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// If likely is set, discard the branch slot if NOT taken.
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void Jit::BranchFPFlag(MIPSOpcode op, Gen::CCFlags cc, bool likely)
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{
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CONDITIONAL_LOG;
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if (js.inDelaySlot) {
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ERROR_LOG_REPORT(JIT, "Branch in FPFlag delay slot at %08x in block starting at %08x", js.compilerPC, js.blockStart);
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return;
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}
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int offset = _IMM16 << 2;
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u32 targetAddr = js.compilerPC + offset + 4;
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MIPSOpcode delaySlotOp = Memory::Read_Instruction(js.compilerPC + 4);
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bool delaySlotIsNice = IsDelaySlotNiceFPU(op, delaySlotOp);
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CONDITIONAL_NICE_DELAYSLOT;
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if (!likely && delaySlotIsNice)
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CompileDelaySlot(DELAYSLOT_NICE);
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TEST(32, M((void *)&(mips_->fpcond)), Imm32(1));
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Gen::FixupBranch ptr;
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RegCacheState state;
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if (!likely)
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{
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if (!delaySlotIsNice)
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CompileDelaySlot(DELAYSLOT_SAFE_FLUSH, state);
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else
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GetStateAndFlushAll(state);
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ptr = J_CC(cc, true);
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}
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else
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{
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GetStateAndFlushAll(state);
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ptr = J_CC(cc, true);
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CompileDelaySlot(DELAYSLOT_FLUSH);
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}
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// Take the branch
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CONDITIONAL_LOG_EXIT(targetAddr);
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WriteExit(targetAddr, js.nextExit++);
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SetJumpTarget(ptr);
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// Not taken
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CONDITIONAL_LOG_EXIT(js.compilerPC + 8);
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if (CanContinueBranch())
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{
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// Account for the delay slot.
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js.compilerPC += 4;
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RestoreState(state);
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// In case the delay slot was a break or something.
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js.compiling = true;
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}
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else
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{
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WriteExit(js.compilerPC + 8, js.nextExit++);
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js.compiling = false;
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}
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}
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void Jit::Comp_FPUBranch(MIPSOpcode op)
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{
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switch((op >> 16) & 0x1f)
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{
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case 0: BranchFPFlag(op, CC_NZ, false); break; //bc1f
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case 1: BranchFPFlag(op, CC_Z, false); break; //bc1t
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case 2: BranchFPFlag(op, CC_NZ, true); break; //bc1fl
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case 3: BranchFPFlag(op, CC_Z, true); break; //bc1tl
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default:
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_dbg_assert_msg_(CPU,0,"Trying to interpret instruction that can't be interpreted");
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break;
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}
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}
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// If likely is set, discard the branch slot if NOT taken.
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void Jit::BranchVFPUFlag(MIPSOpcode op, Gen::CCFlags cc, bool likely)
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{
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CONDITIONAL_LOG;
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if (js.inDelaySlot) {
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ERROR_LOG_REPORT(JIT, "Branch in VFPU delay slot at %08x in block starting at %08x", js.compilerPC, js.blockStart);
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return;
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}
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int offset = _IMM16 << 2;
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u32 targetAddr = js.compilerPC + offset + 4;
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MIPSOpcode delaySlotOp = Memory::Read_Instruction(js.compilerPC + 4);
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// Sometimes there's a VFPU branch in a delay slot (Disgaea 2: Dark Hero Days, Zettai Hero Project, La Pucelle)
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// The behavior is undefined - the CPU may take the second branch even if the first one passes.
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// However, it does consistently try each branch, which these games seem to expect.
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bool delaySlotIsBranch = MIPSCodeUtils::IsVFPUBranch(delaySlotOp);
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bool delaySlotIsNice = !delaySlotIsBranch && IsDelaySlotNiceVFPU(op, delaySlotOp);
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CONDITIONAL_NICE_DELAYSLOT;
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if (!likely && delaySlotIsNice)
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CompileDelaySlot(DELAYSLOT_NICE);
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if (delaySlotIsBranch && (signed short)(delaySlotOp & 0xFFFF) != (signed short)(op & 0xFFFF) - 1)
|
|
ERROR_LOG_REPORT(JIT, "VFPU branch in VFPU delay slot at %08x with different target %d / %d", js.compilerPC, (signed short)(delaySlotOp & 0xFFFF), (signed short)(op & 0xFFFF) - 1);
|
|
|
|
// THE CONDITION
|
|
int imm3 = (op >> 18) & 7;
|
|
|
|
//int val = (mips_->vfpuCtrl[VFPU_CTRL_CC] >> imm3) & 1;
|
|
TEST(32, M((void *)&(mips_->vfpuCtrl[VFPU_CTRL_CC])), Imm32(1 << imm3));
|
|
Gen::FixupBranch ptr;
|
|
RegCacheState state;
|
|
if (!likely)
|
|
{
|
|
if (!delaySlotIsNice && !delaySlotIsBranch)
|
|
CompileDelaySlot(DELAYSLOT_SAFE_FLUSH, state);
|
|
else
|
|
GetStateAndFlushAll(state);
|
|
ptr = J_CC(cc, true);
|
|
}
|
|
else
|
|
{
|
|
GetStateAndFlushAll(state);
|
|
ptr = J_CC(cc, true);
|
|
if (!delaySlotIsBranch)
|
|
CompileDelaySlot(DELAYSLOT_FLUSH);
|
|
}
|
|
|
|
// Take the branch
|
|
CONDITIONAL_LOG_EXIT(targetAddr);
|
|
WriteExit(targetAddr, js.nextExit++);
|
|
|
|
SetJumpTarget(ptr);
|
|
// Not taken
|
|
u32 notTakenTarget = js.compilerPC + (delaySlotIsBranch ? 4 : 8);
|
|
CONDITIONAL_LOG_EXIT(notTakenTarget);
|
|
|
|
if (CanContinueBranch() && !delaySlotIsBranch)
|
|
{
|
|
// Account for the delay slot.
|
|
js.compilerPC += 4;
|
|
RestoreState(state);
|
|
// In case the delay slot was a break or something.
|
|
js.compiling = true;
|
|
}
|
|
else
|
|
{
|
|
WriteExit(notTakenTarget, js.nextExit++);
|
|
js.compiling = false;
|
|
}
|
|
}
|
|
|
|
|
|
void Jit::Comp_VBranch(MIPSOpcode op)
|
|
{
|
|
switch ((op >> 16) & 3)
|
|
{
|
|
case 0: BranchVFPUFlag(op, CC_NZ, false); break; //bvf
|
|
case 1: BranchVFPUFlag(op, CC_Z, false); break; //bvt
|
|
case 2: BranchVFPUFlag(op, CC_NZ, true); break; //bvfl
|
|
case 3: BranchVFPUFlag(op, CC_Z, true); break; //bvtl
|
|
default:
|
|
_dbg_assert_msg_(CPU,0,"Comp_VBranch: Invalid instruction");
|
|
break;
|
|
}
|
|
}
|
|
|
|
void Jit::Comp_Jump(MIPSOpcode op)
|
|
{
|
|
CONDITIONAL_LOG;
|
|
if (js.inDelaySlot) {
|
|
ERROR_LOG_REPORT(JIT, "Branch in Jump delay slot at %08x in block starting at %08x", js.compilerPC, js.blockStart);
|
|
return;
|
|
}
|
|
u32 off = _IMM26 << 2;
|
|
u32 targetAddr = (js.compilerPC & 0xF0000000) | off;
|
|
|
|
switch (op >> 26)
|
|
{
|
|
case 2: //j
|
|
CompileDelaySlot(DELAYSLOT_NICE);
|
|
FlushAll();
|
|
CONDITIONAL_LOG_EXIT(targetAddr);
|
|
WriteExit(targetAddr, js.nextExit++);
|
|
break;
|
|
|
|
case 3: //jal
|
|
gpr.BindToRegister(MIPS_REG_RA, false, true);
|
|
MOV(32, gpr.R(MIPS_REG_RA), Imm32(js.compilerPC + 8)); // Save return address
|
|
CompileDelaySlot(DELAYSLOT_NICE);
|
|
FlushAll();
|
|
CONDITIONAL_LOG_EXIT(targetAddr);
|
|
WriteExit(targetAddr, js.nextExit++);
|
|
break;
|
|
|
|
default:
|
|
_dbg_assert_msg_(CPU,0,"Trying to compile instruction that can't be compiled");
|
|
break;
|
|
}
|
|
js.compiling = false;
|
|
}
|
|
|
|
static u32 savedPC;
|
|
|
|
void Jit::Comp_JumpReg(MIPSOpcode op)
|
|
{
|
|
CONDITIONAL_LOG;
|
|
if (js.inDelaySlot) {
|
|
ERROR_LOG_REPORT(JIT, "Branch in JumpReg delay slot at %08x in block starting at %08x", js.compilerPC, js.blockStart);
|
|
return;
|
|
}
|
|
MIPSGPReg rs = _RS;
|
|
MIPSGPReg rd = _RD;
|
|
|
|
MIPSOpcode delaySlotOp = Memory::Read_Instruction(js.compilerPC + 4);
|
|
bool delaySlotIsNice = IsDelaySlotNiceReg(op, delaySlotOp, rs);
|
|
CONDITIONAL_NICE_DELAYSLOT;
|
|
|
|
if (IsSyscall(delaySlotOp))
|
|
{
|
|
// If this is a syscall, write the pc (for thread switching and other good reasons.)
|
|
gpr.BindToRegister(rs, true, false);
|
|
MOV(32, M(¤tMIPS->pc), gpr.R(rs));
|
|
CompileDelaySlot(DELAYSLOT_FLUSH);
|
|
|
|
// Syscalls write the exit code for us.
|
|
_dbg_assert_msg_(JIT, !js.compiling, "Expected syscall to write an exit code.");
|
|
return;
|
|
}
|
|
else if (delaySlotIsNice)
|
|
{
|
|
CompileDelaySlot(DELAYSLOT_NICE);
|
|
MOV(32, R(EAX), gpr.R(rs));
|
|
|
|
if (rs == MIPS_REG_RA && g_Config.bDiscardRegsOnJRRA) {
|
|
// According to the MIPS ABI, there are some regs we don't need to preserve.
|
|
// Let's discard them so we don't need to write them back.
|
|
// NOTE: Not all games follow the MIPS ABI! Tekken 6, for example, will crash
|
|
// with this enabled.
|
|
for (int i = MIPS_REG_A0; i <= MIPS_REG_T7; i++)
|
|
gpr.DiscardRegContentsIfCached((MIPSGPReg)i);
|
|
gpr.DiscardRegContentsIfCached(MIPS_REG_T8);
|
|
gpr.DiscardRegContentsIfCached(MIPS_REG_T9);
|
|
}
|
|
|
|
FlushAll();
|
|
}
|
|
else
|
|
{
|
|
// Latch destination now - save it in memory.
|
|
gpr.BindToRegister(rs, true, false);
|
|
MOV(32, M(&savedPC), gpr.R(rs));
|
|
CompileDelaySlot(DELAYSLOT_NICE);
|
|
MOV(32, R(EAX), M(&savedPC));
|
|
FlushAll();
|
|
}
|
|
|
|
switch (op & 0x3f)
|
|
{
|
|
case 8: //jr
|
|
break;
|
|
case 9: //jalr
|
|
MOV(32, M(&mips_->r[rd]), Imm32(js.compilerPC + 8));
|
|
break;
|
|
default:
|
|
_dbg_assert_msg_(CPU,0,"Trying to compile instruction that can't be compiled");
|
|
break;
|
|
}
|
|
|
|
CONDITIONAL_LOG_EXIT_EAX();
|
|
WriteExitDestInEAX();
|
|
js.compiling = false;
|
|
}
|
|
|
|
void Jit::Comp_Syscall(MIPSOpcode op)
|
|
{
|
|
FlushAll();
|
|
|
|
// If we're in a delay slot, this is off by one.
|
|
const int offset = js.inDelaySlot ? -1 : 0;
|
|
WriteDowncount(offset);
|
|
js.downcountAmount = -offset;
|
|
|
|
// Skip the CallSyscall where possible.
|
|
void *quickFunc = GetQuickSyscallFunc(op);
|
|
if (quickFunc)
|
|
ABI_CallFunctionP(quickFunc, (void *)GetSyscallInfo(op));
|
|
else
|
|
ABI_CallFunctionC((void *)&CallSyscall, op.encoding);
|
|
|
|
WriteSyscallExit();
|
|
js.compiling = false;
|
|
}
|
|
|
|
void Jit::Comp_Break(MIPSOpcode op)
|
|
{
|
|
Comp_Generic(op);
|
|
WriteSyscallExit();
|
|
js.compiling = false;
|
|
}
|
|
|
|
} // namespace Mipscomp
|