445 lines
12 KiB
C++
445 lines
12 KiB
C++
// Copyright (c) 2012- PPSSPP Project.
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, version 2.0 or later versions.
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License 2.0 for more details.
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// A copy of the GPL 2.0 should have been included with the program.
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// If not, see http://www.gnu.org/licenses/
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// Official git repository and contact information can be found at
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// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
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#include "../../HLE/HLE.h"
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#include "../MIPS.h"
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#include "../MIPSCodeUtils.h"
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#include "../MIPSAnalyst.h"
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#include "../MIPSTables.h"
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#include "ArmJit.h"
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#include "ArmRegCache.h"
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#include "ArmJitCache.h"
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#include <ArmEmitter.h>
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#define _RS ((op>>21) & 0x1F)
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#define _RT ((op>>16) & 0x1F)
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#define _RD ((op>>11) & 0x1F)
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#define _FS ((op>>11) & 0x1F)
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#define _FT ((op>>16) & 0x1F)
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#define _FD ((op>>6 ) & 0x1F)
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#define _POS ((op>>6 ) & 0x1F)
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#define _SIZE ((op>>11 ) & 0x1F)
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#define LOOPOPTIMIZATION 0
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using namespace MIPSAnalyst;
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namespace MIPSComp
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{
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void Jit::BranchRSRTComp(u32 op, ArmGen::CCFlags cc, bool likely)
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{
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if (js.inDelaySlot) {
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ERROR_LOG(JIT, "Branch in delay slot at %08x", js.compilerPC);
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return;
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}
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int offset = (signed short)(op&0xFFFF)<<2;
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int rt = _RT;
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int rs = _RS;
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u32 targetAddr = js.compilerPC + offset + 4;
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u32 delaySlotOp = Memory::ReadUnchecked_U32(js.compilerPC+4);
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//Compile the delay slot
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bool delaySlotIsNice = GetOutReg(delaySlotOp) != rt && GetOutReg(delaySlotOp) != rs;
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if (!delaySlotIsNice)
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{
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//ERROR_LOG(CPU, "Not nice delay slot in BranchRSRTComp :( %08x", js.compilerPC);
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}
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// The delay slot being nice doesn't really matter though...
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if (rt == 0)
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{
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gpr.MapReg(rs);
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CMP(gpr.R(rs), Operand2(0, TYPE_IMM));
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}
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else if (rs == 0 && (cc == CC_EQ || cc == CC_NEQ)) // only these are easily 'flippable'
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{
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gpr.MapReg(rt);
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CMP(gpr.R(rt), Operand2(0, TYPE_IMM));
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}
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else
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{
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gpr.SpillLock(rs, rt);
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gpr.MapReg(rs);
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gpr.MapReg(rt);
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gpr.ReleaseSpillLocks();
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CMP(gpr.R(rs), gpr.R(rt));
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}
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FlushAll();
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js.inDelaySlot = true;
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ArmGen::FixupBranch ptr;
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if (!likely)
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{
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// preserve flag around the delay slot! Maybe this is not always necessary on ARM where
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// we can (mostly) control whether we set the flag or not. Of course, if someone puts an slt in to the
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// delay slot, we're screwed.
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MRS(R8); // Save flags register. R8 is preserved through function calls and is not allocated.
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CompileAt(js.compilerPC + 4);
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FlushAll();
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_MSR(true, false, R8); // Restore flags register
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ptr = B_CC(cc);
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}
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else
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{
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ptr = B_CC(cc);
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CompileAt(js.compilerPC + 4);
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FlushAll();
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}
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js.inDelaySlot = false;
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// Take the branch
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WriteExit(targetAddr, 0);
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SetJumpTarget(ptr);
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// Not taken
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WriteExit(js.compilerPC+8, 1);
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js.compiling = false;
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}
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void Jit::BranchRSZeroComp(u32 op, ArmGen::CCFlags cc, bool andLink, bool likely)
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{
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if (js.inDelaySlot) {
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ERROR_LOG(JIT, "Branch in delay slot at %08x", js.compilerPC);
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return;
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}
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int offset = (signed short)(op&0xFFFF)<<2;
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int rs = _RS;
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u32 targetAddr = js.compilerPC + offset + 4;
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u32 delaySlotOp = Memory::ReadUnchecked_U32(js.compilerPC + 4);
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bool delaySlotIsNice = GetOutReg(delaySlotOp) != rs;
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if (!delaySlotIsNice)
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{
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// ERROR_LOG(CPU, "Not nice delay slot in BranchRSZeroComp :( %08x", js.compilerPC);
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}
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gpr.MapReg(rs);
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CMP(gpr.R(rs), Operand2(0, TYPE_IMM));
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FlushAll();
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ArmGen::FixupBranch ptr;
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js.inDelaySlot = true;
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if (!likely)
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{
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// preserve flag around the delay slot! Maybe this is not always necessary on ARM where
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// we can (mostly) control whether we set the flag or not. Of course, if someone puts an slt in to the
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// delay slot, we're screwed.
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MRS(R8); // Save flags register
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CompileAt(js.compilerPC + 4);
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FlushAll();
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_MSR(true, false, R8); // Restore flags register
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ptr = B_CC(cc);
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}
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else
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{
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ptr = B_CC(cc);
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CompileAt(js.compilerPC + 4);
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FlushAll();
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}
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js.inDelaySlot = false;
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// Take the branch
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if (andLink)
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{
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ADD(R1, R10, MIPS_REG_RA * 4); // compute address of RA in ram
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ARMABI_MOVI2R(R0, js.compilerPC + 8);
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STR(R1, R0);
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}
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WriteExit(targetAddr, 0);
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SetJumpTarget(ptr);
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// Not taken
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WriteExit(js.compilerPC + 8, 1);
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js.compiling = false;
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}
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void Jit::Comp_RelBranch(u32 op)
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{
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// The CC flags here should be opposite of the actual branch becuase they skip the branching action.
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switch (op>>26)
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{
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case 4: BranchRSRTComp(op, CC_NEQ, false); break;//beq
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case 5: BranchRSRTComp(op, CC_EQ, false); break;//bne
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case 6: BranchRSZeroComp(op, CC_GT, false, false); break;//blez
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case 7: BranchRSZeroComp(op, CC_LE, false, false); break;//bgtz
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case 20: BranchRSRTComp(op, CC_NEQ, true); break;//beql
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case 21: BranchRSRTComp(op, CC_EQ, true); break;//bnel
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case 22: BranchRSZeroComp(op, CC_GT, false, true); break;//blezl
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case 23: BranchRSZeroComp(op, CC_LE, false, true); break;//bgtzl
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default:
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_dbg_assert_msg_(CPU,0,"Trying to compile instruction that can't be compiled");
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break;
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}
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js.compiling = false;
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}
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void Jit::Comp_RelBranchRI(u32 op)
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{
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switch ((op >> 16) & 0x1F)
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{
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case 0: BranchRSZeroComp(op, CC_GE, false, false); break; //if ((s32)R(rs) < 0) DelayBranchTo(addr); else PC += 4; break;//bltz
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case 1: BranchRSZeroComp(op, CC_LT, false, false); break; //if ((s32)R(rs) >= 0) DelayBranchTo(addr); else PC += 4; break;//bgez
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case 2: BranchRSZeroComp(op, CC_GE, false, true); break; //if ((s32)R(rs) < 0) DelayBranchTo(addr); else PC += 8; break;//bltzl
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case 3: BranchRSZeroComp(op, CC_LT, false, true); break; //if ((s32)R(rs) >= 0) DelayBranchTo(addr); else PC += 8; break;//bgezl
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case 16: BranchRSZeroComp(op, CC_GE, true, false); break; //R(MIPS_REG_RA) = PC + 8; if ((s32)R(rs) < 0) DelayBranchTo(addr); else PC += 4; break;//bltzal
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case 17: BranchRSZeroComp(op, CC_L, true, false); break; //R(MIPS_REG_RA) = PC + 8; if ((s32)R(rs) >= 0) DelayBranchTo(addr); else PC += 4; break;//bgezal
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case 18: BranchRSZeroComp(op, CC_GE, true, true); break; //R(MIPS_REG_RA) = PC + 8; if ((s32)R(rs) < 0) DelayBranchTo(addr); else SkipLikely(); break;//bltzall
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case 19: BranchRSZeroComp(op, CC_L, true, true); break; //R(MIPS_REG_RA) = PC + 8; if ((s32)R(rs) >= 0) DelayBranchTo(addr); else SkipLikely(); break;//bgezall
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default:
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_dbg_assert_msg_(CPU,0,"Trying to compile instruction that can't be compiled");
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break;
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}
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js.compiling = false;
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}
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// If likely is set, discard the branch slot if NOT taken.
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void Jit::BranchFPFlag(u32 op, ArmGen::CCFlags cc, bool likely)
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{
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if (js.inDelaySlot) {
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ERROR_LOG(JIT, "Branch in delay slot at %08x", js.compilerPC);
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return;
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}
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int offset = (signed short)(op & 0xFFFF) << 2;
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u32 targetAddr = js.compilerPC + offset + 4;
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u32 delaySlotOp = Memory::ReadUnchecked_U32(js.compilerPC + 4);
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bool delaySlotIsNice = IsDelaySlotNice(op, delaySlotOp);
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if (!delaySlotIsNice)
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{
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//ERROR_LOG(CPU, "Not nice delay slot in BranchFPFlag :(");
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}
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FlushAll();
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LDR(R0, R10, offsetof(MIPSState, fpcond));
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TST(R0, Operand2(1, TYPE_IMM));
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ArmGen::FixupBranch ptr;
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js.inDelaySlot = true;
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if (!likely)
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{
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MRS(R8); // Save flags register
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CompileAt(js.compilerPC + 4);
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FlushAll();
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_MSR(true, false, R8); // Restore flags register
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ptr = B_CC(cc);
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}
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else
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{
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ptr = B_CC(cc);
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CompileAt(js.compilerPC + 4);
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FlushAll();
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}
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js.inDelaySlot = false;
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// Take the branch
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WriteExit(targetAddr, 0);
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SetJumpTarget(ptr);
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// Not taken
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WriteExit(js.compilerPC + 8, 1);
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js.compiling = false;
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}
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void Jit::Comp_FPUBranch(u32 op)
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{
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switch((op >> 16) & 0x1f)
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{
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case 0: BranchFPFlag(op, CC_NEQ, false); break; // bc1f
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case 1: BranchFPFlag(op, CC_EQ, false); break; // bc1t
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case 2: BranchFPFlag(op, CC_NEQ, true); break; // bc1fl
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case 3: BranchFPFlag(op, CC_EQ, true); break; // bc1tl
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default:
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_dbg_assert_msg_(CPU,0,"Trying to interpret instruction that can't be interpreted");
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break;
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}
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js.compiling = false;
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}
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// If likely is set, discard the branch slot if NOT taken.
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void Jit::BranchVFPUFlag(u32 op, ArmGen::CCFlags cc, bool likely)
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{
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int offset = (signed short)(op & 0xFFFF) << 2;
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u32 targetAddr = js.compilerPC + offset + 4;
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u32 delaySlotOp = Memory::ReadUnchecked_U32(js.compilerPC + 4);
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bool delaySlotIsNice = IsDelaySlotNice(op, delaySlotOp);
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if (!delaySlotIsNice)
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{
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//ERROR_LOG(CPU, "Not nice delay slot in BranchFPFlag :(");
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}
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FlushAll();
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ARMABI_MOVI2R(R0, (u32)&(mips_->vfpuCtrl[VFPU_CTRL_CC]));
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LDR(R0, R0, Operand2(0, TYPE_IMM));
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int imm3 = (op >> 18) & 7;
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TST(R0, Operand2(1 << imm3, TYPE_IMM));
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ArmGen::FixupBranch ptr;
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js.inDelaySlot = true;
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if (!likely)
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{
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MRS(R8); // Save flags register
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CompileAt(js.compilerPC + 4);
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FlushAll();
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_MSR(true, false, R8); // Restore flags register
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ptr = B_CC(cc);
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}
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else
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{
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ptr = B_CC(cc);
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CompileAt(js.compilerPC + 4);
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FlushAll();
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}
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js.inDelaySlot = false;
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// Take the branch
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WriteExit(targetAddr, 0);
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SetJumpTarget(ptr);
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// Not taken
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WriteExit(js.compilerPC + 8, 1);
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js.compiling = false;
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}
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void Jit::Comp_VBranch(u32 op)
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{
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switch ((op >> 16) & 3)
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{
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case 0: BranchVFPUFlag(op, CC_NEQ, false); break; // bvf
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case 1: BranchVFPUFlag(op, CC_EQ, false); break; // bvt
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case 2: BranchVFPUFlag(op, CC_NEQ, true); break; // bvfl
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case 3: BranchVFPUFlag(op, CC_EQ, true); break; // bvtl
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}
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js.compiling = false;
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}
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void PrintAtExit() {
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INFO_LOG(HLE, "at jump");
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}
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void Jit::Comp_Jump(u32 op)
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{
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if (js.inDelaySlot) {
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ERROR_LOG(JIT, "Branch in delay slot at %08x", js.compilerPC);
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return;
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}
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u32 off = ((op & 0x03FFFFFF) << 2);
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u32 targetAddr = (js.compilerPC & 0xF0000000) | off;
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// Delay slot
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CompileAt(js.compilerPC + 4);
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FlushAll();
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switch (op >> 26)
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{
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case 2: //j
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WriteExit(targetAddr, 0);
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break;
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case 3: //jal
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ADD(R1, R10, MIPS_REG_RA * 4); // compute address of RA in ram
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ARMABI_MOVI2R(R0, js.compilerPC + 8);
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STR(R1, R0);
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WriteExit(targetAddr, 0);
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break;
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default:
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_dbg_assert_msg_(CPU,0,"Trying to compile instruction that can't be compiled");
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break;
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}
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js.compiling = false;
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}
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void Jit::Comp_JumpReg(u32 op)
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{
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if (js.inDelaySlot) {
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ERROR_LOG(JIT, "Branch in delay slot at %08x", js.compilerPC);
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return;
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}
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int rs = _RS;
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u32 delaySlotOp = Memory::ReadUnchecked_U32(js.compilerPC + 4);
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bool delaySlotIsNice = GetOutReg(delaySlotOp) != rs;
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// Do what with that information?
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delaySlotIsNice = false;
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if (delaySlotIsNice) {
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CompileAt(js.compilerPC + 4);
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gpr.MapReg(rs);
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MOV(R8, gpr.R(rs)); // Save the destination address through the delay slot. Could use isNice to avoid when the jit is fully implemented
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FlushAll();
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MovToPC(R8); // For syscall to be able to return. Could be avoided with some checking.
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} else {
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// Delay slot
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gpr.MapReg(rs);
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MOV(R8, gpr.R(rs)); // Save the destination address through the delay slot. Could use isNice to avoid when the jit is fully implemented
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MovToPC(R8); // For syscall to be able to return. Could be avoided with some checking.
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CompileAt(js.compilerPC + 4);
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FlushAll();
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if (!js.compiling) {
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// INFO_LOG(HLE, "Syscall in delay slot!");
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return;
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}
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}
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switch (op & 0x3f)
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{
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case 8: //jr
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break;
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case 9: //jalr
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ADD(R1, R10, MIPS_REG_RA * 4); // compute address of RA in ram
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ARMABI_MOVI2R(R0, js.compilerPC + 8);
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STR(R1, R0);
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break;
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default:
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_dbg_assert_msg_(CPU,0,"Trying to compile instruction that can't be compiled");
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break;
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}
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WriteExitDestInR(R8);
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js.compiling = false;
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}
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void Jit::Comp_Syscall(u32 op)
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{
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FlushAll();
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ARMABI_MOVI2R(R0, op);
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QuickCallFunction(R1, (void *)&CallSyscall);
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WriteSyscallExit();
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js.compiling = false;
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}
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} // namespace Mipscomp
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