312 lines
7.4 KiB
C++
312 lines
7.4 KiB
C++
// Copyright (c) 2023- PPSSPP Project.
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, version 2.0 or later versions.
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License 2.0 for more details.
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// A copy of the GPL 2.0 should have been included with the program.
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// If not, see http://www.gnu.org/licenses/
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// Official git repository and contact information can be found at
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// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
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#include "ppsspp_config.h"
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#if PPSSPP_ARCH(X86) || PPSSPP_ARCH(AMD64)
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#include "Core/MemMap.h"
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#include "Core/MIPS/x86/X64IRJit.h"
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#include "Core/MIPS/x86/X64IRRegCache.h"
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// This file contains compilation for load/store instructions.
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//
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// All functions should have CONDITIONAL_DISABLE, so we can narrow things down to a file quickly.
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// Currently known non working ones should have DISABLE. No flags because that's in IR already.
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// #define CONDITIONAL_DISABLE { CompIR_Generic(inst); return; }
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#define CONDITIONAL_DISABLE {}
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#define DISABLE { CompIR_Generic(inst); return; }
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#define INVALIDOP { _assert_msg_(false, "Invalid IR inst %d", (int)inst.op); CompIR_Generic(inst); return; }
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namespace MIPSComp {
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using namespace Gen;
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using namespace X64IRJitConstants;
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Gen::OpArg X64JitBackend::PrepareSrc1Address(IRInst inst) {
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const IRMeta *m = GetIRMeta(inst.op);
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bool src1IsPointer = regs_.IsGPRMappedAsPointer(inst.src1);
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bool readsFromSrc1 = inst.src1 == inst.src3 && (m->flags & (IRFLAG_SRC3 | IRFLAG_SRC3DST)) != 0;
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// If it's about to be clobbered, don't waste time pointerifying. Use displacement.
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bool clobbersSrc1 = !readsFromSrc1 && regs_.IsGPRClobbered(inst.src1);
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int32_t disp = (int32_t)inst.constant;
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// It can't be this negative, must be a constant address with the top bit set.
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if ((disp & 0xC0000000) == 0x80000000) {
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disp = inst.constant & 0x7FFFFFFF;
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}
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#ifdef MASKED_PSP_MEMORY
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if (disp > 0)
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disp &= Memory::MEMVIEW32_MASK;
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#endif
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OpArg addrArg;
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if (inst.src1 == MIPS_REG_ZERO) {
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#ifdef MASKED_PSP_MEMORY
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disp &= Memory::MEMVIEW32_MASK;
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#endif
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#if PPSSPP_ARCH(AMD64)
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addrArg = MDisp(MEMBASEREG, disp & 0x7FFFFFFF);
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#else
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addrArg = M(Memory::base + disp);
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#endif
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} else if ((jo.cachePointers || src1IsPointer) && !readsFromSrc1 && (!clobbersSrc1 || src1IsPointer)) {
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X64Reg src1 = regs_.MapGPRAsPointer(inst.src1);
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addrArg = MDisp(src1, disp);
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} else {
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regs_.MapGPR(inst.src1);
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#ifdef MASKED_PSP_MEMORY
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LEA(PTRBITS, SCRATCH1, MDisp(regs_.RX(inst.src1), disp));
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AND(PTRBITS, R(SCRATCH1), Imm32(Memory::MEMVIEW32_MASK));
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addrArg = MDisp(SCRATCH1, (intptr_t)Memory::base);
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#else
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#if PPSSPP_ARCH(AMD64)
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addrArg = MComplex(MEMBASEREG, regs_.RX(inst.src1), SCALE_1, disp);
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#else
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addrArg = MDisp(regs_.RX(inst.src1), Memory::base + disp);
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#endif
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#endif
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}
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return addrArg;
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}
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void X64JitBackend::CompIR_CondStore(IRInst inst) {
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CONDITIONAL_DISABLE;
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if (inst.op != IROp::Store32Conditional)
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INVALIDOP;
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regs_.SpillLockGPR(IRREG_LLBIT, inst.src3, inst.src1);
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OpArg addrArg = PrepareSrc1Address(inst);
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OpArg valueArg = R(regs_.MapGPR(inst.src3, MIPSMap::INIT));
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regs_.MapGPR(IRREG_LLBIT, MIPSMap::INIT);
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// TODO: Safe memory? Or enough to have crash handler + validate?
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TEST(32, regs_.R(IRREG_LLBIT), regs_.R(IRREG_LLBIT));
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FixupBranch condFailed = J_CC(CC_Z);
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MOV(32, addrArg, valueArg);
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if (inst.dest != MIPS_REG_ZERO) {
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MOV(32, regs_.R(inst.dest), Imm32(1));
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FixupBranch finish = J();
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SetJumpTarget(condFailed);
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XOR(32, regs_.R(inst.dest), regs_.R(inst.dest));
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SetJumpTarget(finish);
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} else {
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SetJumpTarget(condFailed);
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}
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}
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void X64JitBackend::CompIR_FLoad(IRInst inst) {
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CONDITIONAL_DISABLE;
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OpArg addrArg = PrepareSrc1Address(inst);
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switch (inst.op) {
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case IROp::LoadFloat:
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regs_.MapFPR(inst.dest, MIPSMap::NOINIT);
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MOVSS(regs_.FX(inst.dest), addrArg);
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break;
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default:
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INVALIDOP;
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break;
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}
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}
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void X64JitBackend::CompIR_FStore(IRInst inst) {
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CONDITIONAL_DISABLE;
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OpArg addrArg = PrepareSrc1Address(inst);
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switch (inst.op) {
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case IROp::StoreFloat:
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regs_.MapFPR(inst.src3);
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MOVSS(addrArg, regs_.FX(inst.src3));
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break;
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default:
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INVALIDOP;
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break;
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}
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}
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void X64JitBackend::CompIR_Load(IRInst inst) {
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CONDITIONAL_DISABLE;
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regs_.SpillLockGPR(inst.dest, inst.src1);
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OpArg addrArg = PrepareSrc1Address(inst);
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// With NOINIT, MapReg won't subtract MEMBASEREG even if dest == src1.
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regs_.MapGPR(inst.dest, MIPSMap::NOINIT);
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// TODO: Safe memory? Or enough to have crash handler + validate?
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switch (inst.op) {
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case IROp::Load8:
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MOVZX(32, 8, regs_.RX(inst.dest), addrArg);
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break;
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case IROp::Load8Ext:
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MOVSX(32, 8, regs_.RX(inst.dest), addrArg);
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break;
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case IROp::Load16:
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MOVZX(32, 16, regs_.RX(inst.dest), addrArg);
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break;
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case IROp::Load16Ext:
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MOVSX(32, 16, regs_.RX(inst.dest), addrArg);
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break;
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case IROp::Load32:
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MOV(32, regs_.R(inst.dest), addrArg);
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break;
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case IROp::Load32Linked:
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if (inst.dest != MIPS_REG_ZERO)
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MOV(32, regs_.R(inst.dest), addrArg);
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regs_.SetGPRImm(IRREG_LLBIT, 1);
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break;
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default:
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INVALIDOP;
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break;
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}
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}
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void X64JitBackend::CompIR_LoadShift(IRInst inst) {
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CONDITIONAL_DISABLE;
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switch (inst.op) {
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case IROp::Load32Left:
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case IROp::Load32Right:
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// Should not happen if the pass to split is active.
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DISABLE;
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break;
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default:
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INVALIDOP;
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break;
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}
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}
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void X64JitBackend::CompIR_Store(IRInst inst) {
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CONDITIONAL_DISABLE;
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regs_.SpillLockGPR(inst.src3, inst.src1);
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OpArg addrArg = PrepareSrc1Address(inst);
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// i386 can only use certain regs for 8-bit operations.
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X64Map valueFlags = inst.op == IROp::Store8 ? X64Map::LOW_SUBREG : X64Map::NONE;
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OpArg valueArg;
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X64Reg valueReg = regs_.TryMapTempImm(inst.src3, valueFlags);
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if (valueReg != INVALID_REG) {
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valueArg = R(valueReg);
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} else if (regs_.IsGPRImm(inst.src3)) {
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u32 imm = regs_.GetGPRImm(inst.src3);
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switch (inst.op) {
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case IROp::Store8: valueArg = Imm8((u8)imm); break;
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case IROp::Store16: valueArg = Imm16((u16)imm); break;
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case IROp::Store32: valueArg = Imm32(imm); break;
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default:
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INVALIDOP;
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break;
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}
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} else {
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valueArg = R(regs_.MapGPR(inst.src3, MIPSMap::INIT | valueFlags));
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}
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// TODO: Safe memory? Or enough to have crash handler + validate?
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switch (inst.op) {
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case IROp::Store8:
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MOV(8, addrArg, valueArg);
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break;
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case IROp::Store16:
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MOV(16, addrArg, valueArg);
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break;
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case IROp::Store32:
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MOV(32, addrArg, valueArg);
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break;
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default:
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INVALIDOP;
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break;
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}
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}
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void X64JitBackend::CompIR_StoreShift(IRInst inst) {
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CONDITIONAL_DISABLE;
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switch (inst.op) {
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case IROp::Store32Left:
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case IROp::Store32Right:
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// Should not happen if the pass to split is active.
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DISABLE;
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break;
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default:
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INVALIDOP;
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break;
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}
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}
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void X64JitBackend::CompIR_VecLoad(IRInst inst) {
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CONDITIONAL_DISABLE;
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OpArg addrArg = PrepareSrc1Address(inst);
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switch (inst.op) {
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case IROp::LoadVec4:
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regs_.MapVec4(inst.dest, MIPSMap::NOINIT);
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MOVUPS(regs_.FX(inst.dest), addrArg);
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break;
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default:
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INVALIDOP;
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break;
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}
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}
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void X64JitBackend::CompIR_VecStore(IRInst inst) {
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CONDITIONAL_DISABLE;
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OpArg addrArg = PrepareSrc1Address(inst);
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switch (inst.op) {
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case IROp::StoreVec4:
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regs_.MapVec4(inst.src3);
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MOVUPS(addrArg, regs_.FX(inst.src3));
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break;
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default:
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INVALIDOP;
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break;
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}
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}
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} // namespace MIPSComp
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#endif
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