150 lines
3.3 KiB
Text
150 lines
3.3 KiB
Text
/*
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* Allwinner sun8iw8p1 clk config info.
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* Modified by czy
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*/
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/{
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clocks {
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compatible = "allwinner,sunxi-clk-init";
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device_type = "clocks";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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reg = <0x0 0x01c20000 0x0 0x324>, /*cpux space*/
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<0x0 0x01c20460 0x0 0x4>;
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/* register fixed rate clock*/
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clk_losc: losc {
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#clock-cells = <0>;
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compatible = "allwinner,fixed-clock";
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clock-frequency = <32768>;
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clock-output-names = "losc";
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};
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clk_hosc: hosc {
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#clock-cells = <0>;
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compatible = "allwinner,fixed-clock";
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clock-frequency = <24000000>;
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clock-output-names = "hosc";
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};
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/* register allwinner,sunxi-pll-clock */
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clk_pll_cpu: pll_cpu {
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#clock-cells = <0>;
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compatible = "allwinner,sunxi-pll-clock";
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lock-mode = "new";
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assigned-clock-rates = <528000000>;
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clock-output-names = "pll_cpu";
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};
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clk_pll_ddr0: pll_ddr0 {
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#clock-cells = <0>;
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compatible = "allwinner,sunxi-pll-clock";
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lock-mode = "new";
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assigned-clock-rates = <312000000>; /* 156MHZ */
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clock-output-names = "pll_ddr0";
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};
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clk_pll_ddr1: pll_ddr1 {
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#clock-cells = <0>;
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compatible = "allwinner,sunxi-pll-clock";
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lock-mode = "new";
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clock-output-names = "pll_ddr1";
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};
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clk_pll_periph0: pll_periph0 {
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#clock-cells = <0>;
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compatible = "allwinner,sunxi-pll-clock";
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lock-mode = "new";
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clock-output-names = "pll_periph0";
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};
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clk_pll_periph1: pll_periph1 {
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#clock-cells = <0>;
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compatible = "allwinner,sunxi-pll-clock";
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lock-mode = "new";
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clock-output-names = "pll_periph1";
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};
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/* register allwinner,sunxi-periph-clock */
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clk_cpu: cpu {
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#clock-cells = <0>;
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compatible = "allwinner,sunxi-periph-clock";
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clock-output-names = "cpu";
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};
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clk_axi: axi {
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#clock-cells = <0>;
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compatible = "allwinner,sunxi-periph-clock";
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clock-output-names = "axi";
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};
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clk_ahb0: ahb0 {
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#clock-cells = <0>;
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compatible = "allwinner,sunxi-periph-clock";
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clock-output-names = "ahb0";
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};
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clk_apb0: apb0 {
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#clock-cells = <0>;
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compatible = "allwinner,sunxi-periph-clock";
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clock-output-names = "apb0";
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};
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clk_ahb1: ahb1 {
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#clock-cells = <0>;
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compatible = "allwinner,sunxi-periph-clock";
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clock-output-names = "ahb1";
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};
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clk_apb1: apb1 {
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#clock-cells = <0>;
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compatible = "allwinner,sunxi-periph-clock";
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clock-output-names = "apb1";
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};
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clk_dma: dma {
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#clock-cells = <0>;
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compatible = "allwinner,sunxi-periph-clock";
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clock-output-names = "dma";
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};
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clk_uart0: uart0 {
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#clock-cells = <0>;
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compatible = "allwinner,sunxi-periph-clock";
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clock-output-names = "uart0";
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};
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clk_uart1: uart1 {
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#clock-cells = <0>;
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compatible = "allwinner,sunxi-periph-clock";
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clock-output-names = "uart1";
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};
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clk_pio: pio {
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#clock-cells = <0>;
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compatible = "allwinner,sunxi-periph-clock";
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clock-output-names = "pio";
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};
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clk_hoscx2: hoscx2 {
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#clock-cells = <0>;
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compatible = "allwinner,fixed-factor-clock";
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clocks = <&clk_hosc>;
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clock-mult = <2>;
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clock-div = <1>;
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clock-output-names = "hoscx2";
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};
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clk_pll_periphahb0: pll_periphahb0 {
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#clock-cells = <0>;
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compatible = "allwinner,sunxi-periph-clock";
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clock-output-names = "pll_periphahb0";
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};
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clk_losc_out: losc_out {
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#clock-cells = <0>;
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compatible = "allwinner,sunxi-periph-clock";
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clock-output-names = "losc_out";
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};
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};
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};
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