Implemented ROXL and DIVL for JIT
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ddad4770e7
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2ed5859e5b
13 changed files with 1750 additions and 140 deletions
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@ -107,7 +107,7 @@
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//#define DISABLE_I_LSL
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//#define DISABLE_I_ROL
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//#define DISABLE_I_ROR
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#define DISABLE_I_ROXL
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//#define DISABLE_I_ROXL
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#define DISABLE_I_ROXR
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//#define DISABLE_I_ASRW
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//#define DISABLE_I_ASLW
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@ -125,6 +125,7 @@
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//#define DISABLE_I_DIVU
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//#define DISABLE_I_DIVS
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//#define DISABLE_I_DIVL
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#define RETURN "return 0;"
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@ -1300,6 +1301,47 @@ static void gen_divs(uae_u32 opcode, struct instr *curi, char* ssize) {
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genastore("tmp", curi->dmode, "dstreg", sz_long /*curi->size*/, "dst");
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}
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static void gen_divl(uae_u32 opcode, struct instr *curi, char* ssize) {
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(void) opcode;
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(void) ssize;
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comprintf("\t dont_care_flags();\n");
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comprintf("\t uae_u16 extra=%s;\n", gen_nextiword());
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comprintf("\t int r2=(extra>>12)&7;\n");
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comprintf("\t int r3=extra&7;\n");
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genamode(curi->dmode, "dstreg", curi->size, "dst", 1, 0);
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comprintf("\tregister_possible_exception();\n");
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if (!noflags) {
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comprintf("\t if (extra & 0x0400) {\n"); /* Need full 64 bit divisor */
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comprintf("\t FAIL(1);\n");
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comprintf("\t m68k_pc_offset=m68k_pc_offset_thisinst;\n");
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comprintf("\t " RETURN "\n");
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comprintf("\t } else { \n");
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/* operands in src and r2, result goes into r2, remainder into r3 */
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/* s2 = s2 / src */
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/* s3 = s2 % src */
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comprintf("\t if (extra & 0x0800) { \n"); /* signed */
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comprintf("\t jff_DIVLS32(r2,dst,r3);\n");
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comprintf("\t } else { \n");
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comprintf("\t\t jff_DIVLU32(r2,dst,r3);\n");
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comprintf("\t } \n");
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comprintf("\t }\n");
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comprintf("\t live_flags();\n");
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} else {
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comprintf("\t if (extra & 0x0400) {\n"); /* Need full 64 bit divisor */
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comprintf("\t FAIL(1);\n");
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comprintf("\t m68k_pc_offset=m68k_pc_offset_thisinst;\n");
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comprintf("\t " RETURN "\n");
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comprintf("\t } else {\n");
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comprintf("\t if (extra & 0x0800) { \n"); /* signed */
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comprintf("\t jnf_DIVLS32(r2,dst,r3);\n");
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comprintf("\t } else { \n");
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comprintf("\t\t jnf_DIVLU32(r2,dst,r3);\n");
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comprintf("\t } \n");
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comprintf("\t }\n");
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}
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}
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static void gen_eor(uae_u32 opcode, struct instr *curi, char* ssize) {
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(void) opcode;
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genamode(curi->smode, "srcreg", curi->size, "src", 1, 0);
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@ -1538,7 +1580,6 @@ static void gen_mull(uae_u32 opcode, struct instr *curi, char* ssize) {
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comprintf("\t } \n"); /* The result is in r2/r3, with r2 holding the lower 32 bits */
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comprintf("\t } else {\n"); /* Only want 32 bit result */
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/* operands in dst and r2, result goes into r2 */
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/* shouldn't matter whether it's signed or unsigned?!? */
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comprintf("\t if (extra & 0x0800) { \n"); /* signed */
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comprintf("\t jff_MULS32(r2,dst);\n");
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comprintf("\t } else { \n");
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@ -1557,7 +1598,6 @@ static void gen_mull(uae_u32 opcode, struct instr *curi, char* ssize) {
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comprintf("\t } \n"); /* The result is in r2/r3, with r2 holding the lower 32 bits */
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comprintf("\t } else {\n"); /* Only want 32 bit result */
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/* operands in dst and r2, result foes into r2 */
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/* shouldn't matter whether it's signed or unsigned?!? */
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comprintf("\t if (extra & 0x0800) { \n"); /* signed */
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comprintf("\t jnf_MULS32(r2,dst);\n");
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comprintf("\t } else { \n");
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@ -2716,8 +2756,10 @@ gen_opcode(unsigned long int opcode) {
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break;
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case i_DIVL:
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isjump;
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#ifdef DISABLE_I_DIVL
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failure;
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#endif
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gen_divl(opcode, curi, ssize);
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break;
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case i_MULL:
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@ -3043,7 +3085,7 @@ generate_one_opcode(int rp, int noflags)
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dmsk = 7;
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next_cpu_level = -1;
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if (table68k[opcode].mnemo == i_DIVU || table68k[opcode].mnemo == i_DIVS) {
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if (table68k[opcode].mnemo == i_DIVU || table68k[opcode].mnemo == i_DIVS || table68k[opcode].mnemo == i_DIVL) {
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comprintf("#ifndef ARMV6T2\n");
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comprintf(" FAIL(1);\n");
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comprintf(" " RETURN "\n");
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@ -3141,7 +3183,7 @@ generate_one_opcode(int rp, int noflags)
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if (global_fpu) flags |= 32;
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comprintf ("return 0;\n");
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if (table68k[opcode].mnemo == i_DIVU || table68k[opcode].mnemo == i_DIVS) {
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if (table68k[opcode].mnemo == i_DIVU || table68k[opcode].mnemo == i_DIVS || table68k[opcode].mnemo == i_DIVL) {
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comprintf("#endif\n");
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}
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