Implemented ROXL and DIVL for JIT
This commit is contained in:
Dimitris Panokostas
parent
ddad4770e7
commit
2ed5859e5b
13 changed files with 1750 additions and 140 deletions
22
Makefile
22
Makefile
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@ -23,14 +23,14 @@ CPPFLAGS+= -MD -MP
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#
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ifeq ($(PLATFORM),rpi3)
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CPU_FLAGS += -march=armv8-a -mtune=cortex-a53 -mfpu=neon-fp-armv8
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CFLAGS += ${DISPMANX_FLAGS} -DARMV6T2 -DUSE_ARMNEON -DUSE_SDL1
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CFLAGS += ${DISPMANX_FLAGS} -DARMV6T2 -DUSE_ARMNEON -DARM_HAS_DIV -DUSE_SDL1
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LDFLAGS += ${DISPMANX_LDFLAGS}
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HAVE_NEON = 1
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NAME = amiberry-rpi3-sdl1-dev
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else ifeq ($(PLATFORM),rpi2)
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CPU_FLAGS += -march=armv7-a -mtune=cortex-a7 -mfpu=neon-vfpv4
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CFLAGS += ${DISPMANX_FLAGS} -DARMV6T2 -DUSE_ARMNEON -DUSE_SDL1
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CFLAGS += ${DISPMANX_FLAGS} -DARMV6T2 -DUSE_ARMNEON -DARM_HAS_DIV -DUSE_SDL1
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LDFLAGS += ${DISPMANX_LDFLAGS}
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HAVE_NEON = 1
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NAME = amiberry-rpi2-sdl1-dev
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@ -43,7 +43,7 @@ else ifeq ($(PLATFORM),rpi1)
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else ifeq ($(PLATFORM),android)
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CPU_FLAGS += -mfpu=neon -mfloat-abi=soft
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DEFS += -DANDROIDSDL -DARMV6T2 -DUSE_ARMNEON -DUSE_SDL1
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DEFS += -DANDROIDSDL -DARMV6T2 -DUSE_ARMNEON -DARM_HAS_DIV -DUSE_SDL1
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ANDROID = 1
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HAVE_NEON = 1
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HAVE_SDL_DISPLAY = 1
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@ -55,7 +55,7 @@ else ifeq ($(PLATFORM),android)
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else ifeq ($(PLATFORM),rpi3-sdl2-dispmanx)
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USE_SDL2 = 1
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CPU_FLAGS += -march=armv8-a -mtune=cortex-a53 -mfpu=neon-fp-armv8
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CFLAGS += -DARMV6T2 -DUSE_ARMNEON -DUSE_SDL2 ${DISPMANX_FLAGS}
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CFLAGS += -DARMV6T2 -DUSE_ARMNEON -DARM_HAS_DIV -DUSE_SDL2 ${DISPMANX_FLAGS}
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LDFLAGS += ${DISPMANX_LDFLAGS}
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HAVE_NEON = 1
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NAME = amiberry-rpi3-sdl2-dispmanx-dev
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@ -63,7 +63,7 @@ USE_SDL2 = 1
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else ifeq ($(PLATFORM),rpi2-sdl2-dispmanx)
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USE_SDL2 = 1
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CPU_FLAGS += -march=armv7-a -mtune=cortex-a7 -mfpu=neon-vfpv4
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CFLAGS += -DARMV6T2 -DUSE_ARMNEON -DUSE_SDL2 ${DISPMANX_FLAGS}
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CFLAGS += -DARMV6T2 -DUSE_ARMNEON -DARM_HAS_DIV -DUSE_SDL2 ${DISPMANX_FLAGS}
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LDFLAGS += ${DISPMANX_LDFLAGS}
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HAVE_NEON = 1
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NAME = amiberry-rpi2-sdl2-dispmanx-dev
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@ -81,14 +81,14 @@ USE_SDL2 = 1
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else ifeq ($(PLATFORM),rpi3-sdl2)
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USE_SDL2 = 1
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CPU_FLAGS += -march=armv8-a -mtune=cortex-a53 -mfpu=neon-fp-armv8
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CFLAGS += -DARMV6T2 -DUSE_ARMNEON -DUSE_SDL2
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CFLAGS += -DARMV6T2 -DUSE_ARMNEON -DARM_HAS_DIV -DUSE_SDL2
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HAVE_NEON = 1
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NAME = amiberry-rpi3-sdl2-dev
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else ifeq ($(PLATFORM),rpi2-sdl2)
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USE_SDL2 = 1
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CPU_FLAGS += -march=armv7-a -mtune=cortex-a7 -mfpu=neon-vfpv4
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CFLAGS += -DARMV6T2 -DUSE_ARMNEON -DUSE_SDL2
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CFLAGS += -DARMV6T2 -DUSE_ARMNEON -DARM_HAS_DIV -DUSE_SDL2
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HAVE_NEON = 1
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NAME = amiberry-rpi2-sdl2-dev
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@ -101,7 +101,7 @@ USE_SDL2 = 1
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else ifeq ($(PLATFORM),pine64)
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USE_SDL2 = 1
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CPU_FLAGS += -march=armv7-a -mfpu=vfpv3-d16
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CFLAGS += -DARMV6T2 -D__arm__ -DUSE_SDL2
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CFLAGS += -DARMV6T2 -D__arm__ -DARM_HAS_DIV -DUSE_SDL2
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CC = arm-linux-gnueabihf-gcc
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CXX = arm-linux-gnueabihf-g++
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NAME = amiberry-pine64-sdl2-dev
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@ -109,7 +109,7 @@ USE_SDL2 = 1
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else ifeq ($(PLATFORM),xu4)
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USE_SDL2 = 1
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CPU_FLAGS += -march=armv7ve -mcpu=cortex-a15.cortex-a7 -mtune=cortex-a15.cortex-a7 -mfpu=neon-vfpv4
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CFLAGS += -DARMV6T2 -DUSE_ARMNEON -DUSE_SDL2 -DMALI_GPU -DUSE_RENDER_THREAD
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CFLAGS += -DARMV6T2 -DUSE_ARMNEON -DARM_HAS_DIV -DUSE_SDL2 -DMALI_GPU -DUSE_RENDER_THREAD
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HAVE_NEON = 1
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NAME = amiberry-xu4-dev
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ifdef DEBUG
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@ -121,7 +121,7 @@ USE_SDL2 = 1
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else ifeq ($(PLATFORM),tinker)
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USE_SDL2 = 1
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CPU_FLAGS += -march=armv7-a -mtune=cortex-a17 -mfpu=neon-vfpv4
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CFLAGS += -DARMV6T2 -DUSE_ARMNEON -DUSE_SDL2 -DTINKER -DUSE_RENDER_THREAD -DMALI_GPU -I/usr/local/include
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CFLAGS += -DARMV6T2 -DUSE_ARMNEON -DARM_HAS_DIV -DUSE_SDL2 -DTINKER -DUSE_RENDER_THREAD -DMALI_GPU -I/usr/local/include
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LDFLAGS += -L/usr/local/lib
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HAVE_NEON = 1
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NAME = amiberry-tinker-dev
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@ -129,7 +129,7 @@ USE_SDL2 = 1
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else ifeq ($(PLATFORM),android-sdl2)
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USE_SDL2 = 1
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CPU_FLAGS += -mfpu=neon -mfloat-abi=soft
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DEFS += -DANDROIDSDL -DARMV6T2 -DUSE_ARMNEON -DUSE_SDL2
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DEFS += -DANDROIDSDL -DARMV6T2 -DUSE_ARMNEON -DARM_HAS_DIV -DUSE_SDL2
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ANDROID = 1
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HAVE_NEON = 1
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HAVE_SDL_DISPLAY = 1
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@ -62,8 +62,8 @@
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#include "guisan/platform.hpp"
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#ifdef _MSC_VER
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#if _MSC_VER <= 1200
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#ifdef _MSC_VER_
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#if _MSC_VER_ <= 1200
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#define __FUNCTION__ "?"
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#endif
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#endif
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@ -20,5 +20,3 @@
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#if defined(CPU_i386) || defined(CPU_x86_64)
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extern void init_fpucw_x87(void);
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#endif
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extern void fpsr_set_exception(uae_u32 exception);
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@ -7,6 +7,17 @@
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#include "uae/types.h"
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#include <string.h>
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#ifdef _WIN32_
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/* Make sure the real _tcs* functions are already declared before we
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* re-define them below. */
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#include <tchar.h>
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#include <wchar.h>
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#include <stdlib.h>
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#endif
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#ifdef _WIN32_
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/* Using the real _tcs* functions */
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#else
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#define _istdigit isdigit
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#define _istspace isspace
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#define _istupper isupper
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@ -42,6 +53,7 @@
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#define _tstol atol
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#define _vsnprintf vsnprintf
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#define _vsntprintf vsnprintf
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#endif
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static size_t uae_tcslcpy(char *dst, const TCHAR *src, size_t size)
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{
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@ -53,8 +53,17 @@ typedef uae_u32 uaecptr;
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typedef char uae_char;
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#ifdef _WIN32_
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#include <tchar.h>
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#ifdef UNICODE
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#define SIZEOF_TCHAR 2
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#else
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#define SIZEOF_TCHAR 1
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#endif
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#else
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typedef char TCHAR;
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#define SIZEOF_TCHAR 1
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#endif
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#ifndef _T
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#if SIZEOF_TCHAR == 1
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@ -1341,6 +1341,12 @@ enum {
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#define CC_SSAT_rir(cc,Rd,i,Rn) _W(((cc) << 28) | (0x6a << 20) | (i << 16) | (Rd << 12) | (0x1 << 4) | (Rn))
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#define SSAT_rir(Rd,i,Rn) CC_SSAT_rir(NATIVE_CC_AL,Rd,i,Rn)
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#define CC_SDIV_rrr(cc,Rd,Rn,Rm) _W(((cc) << 28) | (0x7 << 24) | (0x1 << 20) | (Rd << 16) | (0xf << 12) | (Rm << 8) | (0x1 << 4) | (Rn))
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#define SDIV_rrr(Rd,Rn,Rm) CC_SDIV_rrr(NATIVE_CC_AL,Rd,Rn,Rm)
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#define CC_UDIV_rrr(cc,Rd,Rn,Rm) _W(((cc) << 28) | (0x7 << 24) | (0x3 << 20) | (Rd << 16) | (0xf << 12) | (Rm << 8) | (0x1 << 4) | (Rn))
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#define UDIV_rrr(Rd,Rn,Rm) CC_UDIV_rrr(NATIVE_CC_AL,Rd,Rn,Rm)
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//#endif
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// Floatingpoint
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1089
src/jit/compemu.cpp
1089
src/jit/compemu.cpp
File diff suppressed because it is too large
Load diff
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@ -1860,7 +1860,7 @@ MENDFUNC(2,jff_DBCC,(RR2 d, IMM cc))
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UNSIGNED16_REG_2_REG(REG_WORK3, s2);
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TST_rr(REG_WORK3, REG_WORK3);
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BNE_i(6); // src is not 0
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BNE_i(4); // src is not 0
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// Signal exception 5
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MOV_ri(REG_WORK1, 5);
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@ -1872,10 +1872,12 @@ MENDFUNC(2,jff_DBCC,(RR2 d, IMM cc))
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LDR_rRI(REG_WORK2, RPC_INDEX, offs);
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#endif
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STR_rR(REG_WORK1, REG_WORK2);
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#ifdef ARM_HAS_DIV
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B_i(5); // end_of_op
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// simplified flag handling for div0: set Z and V (for signed DIV: Z only)
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MOV_ri(REG_WORK1, ARM_Z_FLAG | ARM_V_FLAG);
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MSR_CPSRf_r(REG_WORK1);
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// src is not 0
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UDIV_rrr(REG_WORK1, s1, REG_WORK3);
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#else
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B_i(11); // end_of_op
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// src is not 0
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@ -1886,11 +1888,12 @@ MENDFUNC(2,jff_DBCC,(RR2 d, IMM cc))
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VDIV64_ddd(SCRATCH_F64_3, SCRATCH_F64_1, SCRATCH_F64_2);
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VCVT64toIu_sd(SCRATCH_F32_1, SCRATCH_F64_3);
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VMOVi_to_ARM_rd(REG_WORK1, SCRATCH_F64_1, 0);
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#endif
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LSRS_rri(REG_WORK2, REG_WORK1, 16); // if result of this is not 0, DIVU overflows -> no result
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BNE_i(2);
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// Here we have to calc reminder
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// Here we have to calc remainder
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MUL_rrr(REG_WORK2, REG_WORK1, REG_WORK3);
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SUB_rrr(REG_WORK2, s1, REG_WORK2);
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PKHBT_rrrLSLi(d, REG_WORK1, REG_WORK2, 16);
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@ -1926,6 +1929,12 @@ MIDFUNC(3,jff_DIVU,(W4 d, RR4 s1, RR4 s2))
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// simplified flag handling for div0: set Z and V (for signed DIV: Z only)
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MOV_ri(REG_WORK1, ARM_Z_FLAG | ARM_V_FLAG);
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MSR_CPSRf_r(REG_WORK1);
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#ifdef ARM_HAS_DIV
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B_i(12); // end_of_op
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// src is not 0
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UDIV_rrr(REG_WORK1, s1, REG_WORK3);
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#else
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B_i(18); // end_of_op
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// src is not 0
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@ -1936,6 +1945,7 @@ MIDFUNC(3,jff_DIVU,(W4 d, RR4 s1, RR4 s2))
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VDIV64_ddd(SCRATCH_F64_3, SCRATCH_F64_1, SCRATCH_F64_2);
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VCVT64toIu_sd(SCRATCH_F32_1, SCRATCH_F64_3);
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VMOVi_to_ARM_rd(REG_WORK1, SCRATCH_F64_1, 0);
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#endif
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LSRS_rri(REG_WORK2, REG_WORK1, 16); // if result of this is not 0, DIVU overflows
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BEQ_i(2);
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@ -1944,7 +1954,7 @@ MIDFUNC(3,jff_DIVU,(W4 d, RR4 s1, RR4 s2))
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MSR_CPSRf_r(REG_WORK1);
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B_i(6);
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// Here we have to calc flags and reminder
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// Here we have to calc flags and remainder
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LSLS_rri(REG_WORK2, REG_WORK1, 16); // N and Z ok
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MRS_CPSR(REG_WORK2);
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BIC_rri(REG_WORK2, REG_WORK2, ARM_C_FLAG | ARM_V_FLAG);
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@ -1979,7 +1989,7 @@ MIDFUNC(3,jnf_DIVS,(W4 d, RR4 s1, RR4 s2))
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SIGNED16_REG_2_REG(REG_WORK3, s2);
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TST_rr(REG_WORK3, REG_WORK3);
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BNE_i(6); // src is not 0
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BNE_i(4); // src is not 0
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// Signal exception 5
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MOV_ri(REG_WORK1, 5);
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@ -1991,10 +2001,12 @@ MIDFUNC(3,jnf_DIVS,(W4 d, RR4 s1, RR4 s2))
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LDR_rRI(REG_WORK2, RPC_INDEX, offs);
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#endif
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STR_rR(REG_WORK1, REG_WORK2);
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#ifdef ARM_HAS_DIV
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B_i(12); // end_of_op
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// simplified flag handling for div0: set Z and V (for signed DIV: Z only)
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MOV_ri(REG_WORK1, ARM_Z_FLAG);
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MSR_CPSRf_r(REG_WORK1);
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// src is not 0
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SDIV_rrr(REG_WORK1, s1, REG_WORK3);
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#else
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B_i(18); // end_of_op
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// src is not 0
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@ -2005,6 +2017,7 @@ MIDFUNC(3,jnf_DIVS,(W4 d, RR4 s1, RR4 s2))
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VDIV64_ddd(SCRATCH_F64_3, SCRATCH_F64_1, SCRATCH_F64_2);
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VCVT64toI_sd(SCRATCH_F32_1, SCRATCH_F64_3);
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VMOVi_to_ARM_rd(REG_WORK1, SCRATCH_F64_1, 0);
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#endif
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// check for overflow
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MVN_ri(REG_WORK2, 0);
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@ -2014,7 +2027,7 @@ MIDFUNC(3,jnf_DIVS,(W4 d, RR4 s1, RR4 s2))
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CMP_rr(REG_WORK3, REG_WORK2);
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BNE_i(5); // overflow -> end_of_op
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// Here we have to calc reminder
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// Here we have to calc remainder
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SIGNED16_REG_2_REG(REG_WORK3, s2);
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MUL_rrr(REG_WORK2, REG_WORK1, REG_WORK3);
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SUB_rrr(REG_WORK2, s1, REG_WORK2); // REG_WORK2 contains remainder
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@ -2055,6 +2068,12 @@ MIDFUNC(3,jff_DIVS,(W4 d, RR4 s1, RR4 s2))
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// simplified flag handling for div0: set Z and V (for signed DIV: Z only)
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MOV_ri(REG_WORK1, ARM_Z_FLAG);
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MSR_CPSRf_r(REG_WORK1);
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#ifdef ARM_HAS_DIV
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B_i(19); // end_of_op
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// src is not 0
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SDIV_rrr(REG_WORK1, s1, REG_WORK3);
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#else
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B_i(25); // end_of_op
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// src is not 0
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@ -2065,6 +2084,7 @@ MIDFUNC(3,jff_DIVS,(W4 d, RR4 s1, RR4 s2))
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VDIV64_ddd(SCRATCH_F64_3, SCRATCH_F64_1, SCRATCH_F64_2);
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VCVT64toI_sd(SCRATCH_F32_1, SCRATCH_F64_3);
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VMOVi_to_ARM_rd(REG_WORK1, SCRATCH_F64_1, 0);
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#endif
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// check for overflow
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MVN_ri(REG_WORK2, 0);
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@ -2103,6 +2123,201 @@ MIDFUNC(3,jff_DIVS,(W4 d, RR4 s1, RR4 s2))
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}
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MENDFUNC(3,jff_DIVS,(W4 d, RR4 s1, RR4 s2))
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MIDFUNC(3,jnf_DIVLU32,(RW4 d, RR4 s1, W4 rem))
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{
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s1 = readreg(s1, 4);
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d = rmw(d, 4, 4);
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rem = writereg(rem, 4);
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TST_rr(s1, s1);
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BNE_i(4); // src is not 0
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// Signal exception 5
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MOV_ri(REG_WORK1, 5);
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MOVW_ri16(REG_WORK2, (uae_u32)(&jit_exception));
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MOVT_ri16(REG_WORK2, ((uae_u32)(&jit_exception)) >> 16);
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STR_rR(REG_WORK1, REG_WORK2);
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#ifdef ARM_HAS_DIV
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B_i(3); // end_of_op
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// src is not 0
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UDIV_rrr(REG_WORK1, d, s1);
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#else
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B_i(9); // end_of_op
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// src is not 0
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VMOVi_from_ARM_dr(SCRATCH_F64_1, d, 0);
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VMOVi_from_ARM_dr(SCRATCH_F64_2, s1, 0);
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VCVTIuto64_ds(SCRATCH_F64_1, SCRATCH_F32_1);
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VCVTIuto64_ds(SCRATCH_F64_2, SCRATCH_F32_2);
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VDIV64_ddd(SCRATCH_F64_3, SCRATCH_F64_1, SCRATCH_F64_2);
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VCVT64toIu_sd(SCRATCH_F32_1, SCRATCH_F64_3);
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VMOVi_to_ARM_rd(REG_WORK1, SCRATCH_F64_1, 0);
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#endif
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// Here we have to calc remainder
|
||||
MUL_rrr(REG_WORK2, s1, REG_WORK1);
|
||||
SUB_rrr(rem, d, REG_WORK2);
|
||||
MOV_rr(d, REG_WORK1);
|
||||
|
||||
// end_of_op
|
||||
|
||||
unlock2(rem);
|
||||
unlock2(d);
|
||||
unlock2(s1);
|
||||
}
|
||||
MENDFUNC(3,jnf_DIVLU32,(RW4 d, RR4 s1, W4 rem))
|
||||
|
||||
MIDFUNC(3,jff_DIVLU32,(RW4 d, RR4 s1, W4 rem))
|
||||
{
|
||||
s1 = readreg(s1, 4);
|
||||
d = rmw(d, 4, 4);
|
||||
rem = writereg(rem, 4);
|
||||
|
||||
TST_rr(s1, s1);
|
||||
BNE_i(6); // src is not 0
|
||||
|
||||
// Signal exception 5
|
||||
MOV_ri(REG_WORK1, 5);
|
||||
MOVW_ri16(REG_WORK2, (uae_u32)(&jit_exception));
|
||||
MOVT_ri16(REG_WORK2, ((uae_u32)(&jit_exception)) >> 16);
|
||||
STR_rR(REG_WORK1, REG_WORK2);
|
||||
|
||||
// simplified flag handling for div0: set Z and V (for signed DIV: Z only)
|
||||
MOV_ri(REG_WORK1, ARM_Z_FLAG);
|
||||
MSR_CPSRf_r(REG_WORK1);
|
||||
#ifdef ARM_HAS_DIV
|
||||
B_i(7); // end_of_op
|
||||
|
||||
// src is not 0
|
||||
UDIV_rrr(REG_WORK1, d, s1);
|
||||
#else
|
||||
B_i(13); // end_of_op
|
||||
|
||||
// src is not 0
|
||||
VMOVi_from_ARM_dr(SCRATCH_F64_1, d, 0);
|
||||
VMOVi_from_ARM_dr(SCRATCH_F64_2, s1, 0);
|
||||
VCVTIuto64_ds(SCRATCH_F64_1, SCRATCH_F32_1);
|
||||
VCVTIuto64_ds(SCRATCH_F64_2, SCRATCH_F32_2);
|
||||
VDIV64_ddd(SCRATCH_F64_3, SCRATCH_F64_1, SCRATCH_F64_2);
|
||||
VCVT64toIu_sd(SCRATCH_F32_1, SCRATCH_F64_3);
|
||||
VMOVi_to_ARM_rd(REG_WORK1, SCRATCH_F64_1, 0);
|
||||
#endif
|
||||
|
||||
// Here we have to calc flags and remainder
|
||||
TST_rr(REG_WORK1, REG_WORK1);
|
||||
MRS_CPSR(REG_WORK2);
|
||||
BIC_rri(REG_WORK2, REG_WORK2, ARM_C_FLAG | ARM_V_FLAG);
|
||||
MSR_CPSRf_r(REG_WORK2);
|
||||
|
||||
MUL_rrr(REG_WORK2, s1, REG_WORK1);
|
||||
SUB_rrr(rem, d, REG_WORK2);
|
||||
MOV_rr(d, REG_WORK1);
|
||||
|
||||
// end_of_op
|
||||
|
||||
unlock2(rem);
|
||||
unlock2(d);
|
||||
unlock2(s1);
|
||||
}
|
||||
MENDFUNC(3,jff_DIVLU32,(RW4 d, RR4 s1, W4 rem))
|
||||
|
||||
MIDFUNC(3,jnf_DIVLS32,(RW4 d, RR4 s1, W4 rem))
|
||||
{
|
||||
s1 = readreg(s1, 4);
|
||||
d = rmw(d, 4, 4);
|
||||
rem = writereg(rem, 4);
|
||||
|
||||
TST_rr(s1, s1);
|
||||
BNE_i(4); // src is not 0
|
||||
|
||||
// Signal exception 5
|
||||
MOV_ri(REG_WORK1, 5);
|
||||
MOVW_ri16(REG_WORK2, (uae_u32)(&jit_exception));
|
||||
MOVT_ri16(REG_WORK2, ((uae_u32)(&jit_exception)) >> 16);
|
||||
STR_rR(REG_WORK1, REG_WORK2);
|
||||
#ifdef ARM_HAS_DIV
|
||||
B_i(5); // end_of_op
|
||||
|
||||
// src is not 0
|
||||
SDIV_rrr(REG_WORK1, d, s1);
|
||||
#else
|
||||
B_i(11); // end_of_op
|
||||
|
||||
// src is not 0
|
||||
VMOVi_from_ARM_dr(SCRATCH_F64_1, d, 0);
|
||||
VMOVi_from_ARM_dr(SCRATCH_F64_2, s1, 0);
|
||||
VCVTIto64_ds(SCRATCH_F64_1, SCRATCH_F32_1);
|
||||
VCVTIto64_ds(SCRATCH_F64_2, SCRATCH_F32_2);
|
||||
VDIV64_ddd(SCRATCH_F64_3, SCRATCH_F64_1, SCRATCH_F64_2);
|
||||
VCVT64toI_sd(SCRATCH_F32_1, SCRATCH_F64_3);
|
||||
VMOVi_to_ARM_rd(REG_WORK1, SCRATCH_F64_1, 0);
|
||||
#endif
|
||||
|
||||
// Here we have to calc remainder
|
||||
MUL_rrr(REG_WORK2, s1, REG_WORK1);
|
||||
SUB_rrr(rem, d, REG_WORK2);
|
||||
|
||||
EORS_rrr(REG_WORK3, rem, d); // If sign of remainder and first operand differs, change sign of remainder
|
||||
CC_RSB_rri(NATIVE_CC_MI, rem, rem, 0);
|
||||
MOV_rr(d, REG_WORK1);
|
||||
|
||||
// end_of_op
|
||||
|
||||
unlock2(rem);
|
||||
unlock2(d);
|
||||
unlock2(s1);
|
||||
}
|
||||
MENDFUNC(3,jnf_DIVLS32,(RW4 d, RR4 s1, W4 rem))
|
||||
|
||||
MIDFUNC(3,jff_DIVLS32,(RW4 d, RR4 s1, W4 rem))
|
||||
{
|
||||
s1 = readreg(s1, 4);
|
||||
d = rmw(d, 4, 4);
|
||||
rem = writereg(rem, 4);
|
||||
|
||||
TST_rr(s1, s1);
|
||||
BNE_i(4); // src is not 0
|
||||
|
||||
// Signal exception 5
|
||||
MOV_ri(REG_WORK1, 5);
|
||||
MOVW_ri16(REG_WORK2, (uae_u32)(&jit_exception));
|
||||
MOVT_ri16(REG_WORK2, ((uae_u32)(&jit_exception)) >> 16);
|
||||
STR_rR(REG_WORK1, REG_WORK2);
|
||||
#ifdef ARM_HAS_DIV
|
||||
B_i(3); // end_of_op
|
||||
|
||||
// src is not 0
|
||||
SDIV_rrr(REG_WORK1, d, s1);
|
||||
#else
|
||||
B_i(9); // end_of_op
|
||||
|
||||
// src is not 0
|
||||
VMOVi_from_ARM_dr(SCRATCH_F64_1, d, 0);
|
||||
VMOVi_from_ARM_dr(SCRATCH_F64_2, s1, 0);
|
||||
VCVTIto64_ds(SCRATCH_F64_1, SCRATCH_F32_1);
|
||||
VCVTIto64_ds(SCRATCH_F64_2, SCRATCH_F32_2);
|
||||
VDIV64_ddd(SCRATCH_F64_3, SCRATCH_F64_1, SCRATCH_F64_2);
|
||||
VCVT64toI_sd(SCRATCH_F32_1, SCRATCH_F64_3);
|
||||
VMOVi_to_ARM_rd(REG_WORK1, SCRATCH_F64_1, 0);
|
||||
#endif
|
||||
|
||||
// Here we have to calc remainder
|
||||
MUL_rrr(REG_WORK2, s1, REG_WORK1);
|
||||
SUB_rrr(rem, d, REG_WORK2);
|
||||
|
||||
EORS_rrr(REG_WORK3, rem, d); // If sign of remainder and first operand differs, change sign of remainder
|
||||
CC_RSB_rri(NATIVE_CC_MI, rem, rem, 0);
|
||||
MOV_rr(d, REG_WORK1);
|
||||
|
||||
// end_of_op
|
||||
|
||||
unlock2(rem);
|
||||
unlock2(d);
|
||||
unlock2(s1);
|
||||
}
|
||||
MENDFUNC(3,jff_DIVLS32,(RW4 d, RR4 s1, W4 rem))
|
||||
|
||||
/*
|
||||
* EOR
|
||||
* Operand Syntax: Dn, <ea>
|
||||
|
|
@ -4159,63 +4374,263 @@ MENDFUNC(2,jff_ROLW,(W4 d, RR4 s))
|
|||
* C Set according to the last bit rotated out of the operand. Cleared when the rotate count is zero.
|
||||
*
|
||||
*/
|
||||
MIDFUNC(3,jnf_ROXL_b_imm,(W4 d, RR4 s, IMM i))
|
||||
{
|
||||
}
|
||||
MENDFUNC(3,jnf_ROXL_b_imm,(W4 d, RR4 s, IMM i))
|
||||
|
||||
MIDFUNC(3,jnf_ROXL_w_imm,(W4 d, RR4 s, IMM i))
|
||||
{
|
||||
}
|
||||
MENDFUNC(3,jnf_ROXL_w_imm,(W4 d, RR4 s, IMM i))
|
||||
|
||||
MIDFUNC(3,jnf_ROXL_l_imm,(W4 d, RR4 s, IMM i))
|
||||
{
|
||||
}
|
||||
MENDFUNC(3,jnf_ROXL_l_imm,(W4 d, RR4 s, IMM i))
|
||||
|
||||
MIDFUNC(3,jff_ROXL_b_imm,(W4 d, RR4 s, IMM i))
|
||||
{
|
||||
}
|
||||
MENDFUNC(3,jff_ROXL_b_imm,(W4 d, RR4 s, IMM i))
|
||||
|
||||
MIDFUNC(3,jff_ROXL_w_imm,(W4 d, RR4 s, IMM i))
|
||||
{
|
||||
}
|
||||
MENDFUNC(3,jff_ROXL_w_imm,(W4 d, RR4 s, IMM i))
|
||||
|
||||
MIDFUNC(3,jff_ROXL_l_imm,(W4 d, RR4 s, IMM i))
|
||||
{
|
||||
}
|
||||
MENDFUNC(3,jff_ROXL_l_imm,(W4 d, RR4 s, IMM i))
|
||||
|
||||
MIDFUNC(3,jnf_ROXL_b,(W4 d, RR4 s, RR4 i))
|
||||
{
|
||||
i = readreg(i, 4);
|
||||
s = readreg(s, 4);
|
||||
int x = readreg(FLAGX, 4);
|
||||
d = writereg(d, 4);
|
||||
|
||||
clobber_flags();
|
||||
|
||||
AND_rri(REG_WORK1, i, 63);
|
||||
CMP_ri(REG_WORK1, 35);
|
||||
CC_SUB_rri(NATIVE_CC_GT, REG_WORK1, REG_WORK1, 36);
|
||||
CMP_ri(REG_WORK1, 17);
|
||||
CC_SUB_rri(NATIVE_CC_GT, REG_WORK1, REG_WORK1, 18);
|
||||
CMP_ri(REG_WORK1, 8);
|
||||
CC_SUB_rri(NATIVE_CC_GT, REG_WORK1, REG_WORK1, 9);
|
||||
TST_rr(REG_WORK1, REG_WORK1);
|
||||
CC_MOV_rr(NATIVE_CC_EQ, d, s);
|
||||
BEQ_i(7); // end of op
|
||||
|
||||
// need to rotate
|
||||
CMP_ri(REG_WORK1, 8);
|
||||
CC_MOV_rrLSLr(NATIVE_CC_NE, REG_WORK2, s, REG_WORK1);
|
||||
CC_MOV_ri(NATIVE_CC_EQ, REG_WORK2, 0);
|
||||
|
||||
SUB_rri(REG_WORK3, REG_WORK1, 1);
|
||||
ORR_rrrLSLr(REG_WORK2, REG_WORK2, x, REG_WORK3);
|
||||
|
||||
RSB_rri(REG_WORK3, REG_WORK1, 9);
|
||||
UNSIGNED8_REG_2_REG(REG_WORK1, s);
|
||||
ORR_rrrLSRr(d, REG_WORK2, REG_WORK1, REG_WORK3);
|
||||
|
||||
// end of op
|
||||
|
||||
unlock2(x);
|
||||
unlock2(d);
|
||||
unlock2(s);
|
||||
unlock2(i);
|
||||
}
|
||||
MENDFUNC(3,jnf_ROXL_b,(W4 d, RR4 s, RR4 i))
|
||||
|
||||
MIDFUNC(3,jnf_ROXL_w,(W4 d, RR4 s, RR4 i))
|
||||
{
|
||||
i = readreg(i, 4);
|
||||
s = readreg(s, 4);
|
||||
int x = readreg(FLAGX, 4);
|
||||
d = writereg(d, 4);
|
||||
|
||||
clobber_flags();
|
||||
|
||||
AND_rri(REG_WORK1, i, 63);
|
||||
CMP_ri(REG_WORK1, 33);
|
||||
CC_SUB_rri(NATIVE_CC_GT, REG_WORK1, REG_WORK1, 34);
|
||||
CMP_ri(REG_WORK1, 16);
|
||||
CC_SUB_rri(NATIVE_CC_GT, REG_WORK1, REG_WORK1, 17);
|
||||
TST_rr(REG_WORK1, REG_WORK1);
|
||||
CC_MOV_rr(NATIVE_CC_EQ, d, s);
|
||||
BEQ_i(7); // end of op
|
||||
|
||||
// need to rotate
|
||||
CMP_ri(REG_WORK1, 16);
|
||||
CC_MOV_rrLSLr(NATIVE_CC_NE, REG_WORK2, s, REG_WORK1);
|
||||
CC_MOV_ri(NATIVE_CC_EQ, REG_WORK2, 0);
|
||||
|
||||
SUB_rri(REG_WORK3, REG_WORK1, 1);
|
||||
ORR_rrrLSLr(REG_WORK2, REG_WORK2, x, REG_WORK3);
|
||||
|
||||
RSB_rri(REG_WORK3, REG_WORK1, 17);
|
||||
UNSIGNED16_REG_2_REG(REG_WORK1, s);
|
||||
ORR_rrrLSRr(d, REG_WORK2, REG_WORK1, REG_WORK3);
|
||||
|
||||
// end of op
|
||||
|
||||
unlock2(x);
|
||||
unlock2(d);
|
||||
unlock2(s);
|
||||
unlock2(i);
|
||||
}
|
||||
MENDFUNC(3,jnf_ROXL_w,(W4 d, RR4 s, RR4 i))
|
||||
|
||||
MIDFUNC(3,jnf_ROXL_l,(W4 d, RR4 s, RR4 i))
|
||||
{
|
||||
i = readreg(i, 4);
|
||||
s = readreg(s, 4);
|
||||
int x = readreg(FLAGX, 4);
|
||||
d = writereg(d, 4);
|
||||
|
||||
clobber_flags();
|
||||
|
||||
AND_rri(REG_WORK1, i, 63);
|
||||
CMP_ri(REG_WORK1, 32);
|
||||
CC_SUB_rri(NATIVE_CC_GT, REG_WORK1, REG_WORK1, 33);
|
||||
TST_rr(REG_WORK1, REG_WORK1);
|
||||
CC_MOV_rr(NATIVE_CC_EQ, d, s);
|
||||
BEQ_i(6); // end of op
|
||||
|
||||
// need to rotate
|
||||
CMP_ri(REG_WORK1, 32);
|
||||
CC_MOV_rrLSLr(NATIVE_CC_NE, REG_WORK2, s, REG_WORK1);
|
||||
CC_MOV_ri(NATIVE_CC_EQ, REG_WORK2, 0);
|
||||
|
||||
SUB_rri(REG_WORK3, REG_WORK1, 1);
|
||||
ORR_rrrLSLr(REG_WORK2, REG_WORK2, x, REG_WORK3);
|
||||
|
||||
RSB_rri(REG_WORK3, REG_WORK1, 33);
|
||||
ORR_rrrLSRr(d, REG_WORK2, s, REG_WORK3);
|
||||
|
||||
// end of op
|
||||
|
||||
unlock2(x);
|
||||
unlock2(d);
|
||||
unlock2(s);
|
||||
unlock2(i);
|
||||
}
|
||||
MENDFUNC(3,jnf_ROXL_l,(W4 d, RR4 s, RR4 i))
|
||||
|
||||
MIDFUNC(3,jff_ROXL_b,(W4 d, RR4 s, RR4 i))
|
||||
{
|
||||
i = readreg(i, 4);
|
||||
s = readreg(s, 4);
|
||||
int x = rmw(FLAGX, 4, 4);
|
||||
d = writereg(d, 4);
|
||||
|
||||
AND_rri(REG_WORK1, i, 63);
|
||||
CMP_ri(REG_WORK1, 35);
|
||||
CC_SUB_rri(NATIVE_CC_GT, REG_WORK1, REG_WORK1, 36);
|
||||
CMP_ri(REG_WORK1, 17);
|
||||
CC_SUB_rri(NATIVE_CC_GT, REG_WORK1, REG_WORK1, 18);
|
||||
CMP_ri(REG_WORK1, 8);
|
||||
CC_SUB_rri(NATIVE_CC_GT, REG_WORK1, REG_WORK1, 9);
|
||||
TST_rr(REG_WORK1, REG_WORK1);
|
||||
BNE_i(3); // need to rotate
|
||||
|
||||
MSR_CPSRf_i(0);
|
||||
MOVS_rrLSLi(d, s, 24);
|
||||
LSR_rri(d, d, 24);
|
||||
B_i(12); // end of op
|
||||
|
||||
// need to rotate
|
||||
CMP_ri(REG_WORK1, 8);
|
||||
CC_MOV_rrLSLr(NATIVE_CC_NE, REG_WORK2, s, REG_WORK1);
|
||||
CC_MOV_ri(NATIVE_CC_EQ, REG_WORK2, 0);
|
||||
|
||||
SUB_rri(REG_WORK3, REG_WORK1, 1);
|
||||
ORR_rrrLSLr(REG_WORK2, REG_WORK2, x, REG_WORK3);
|
||||
|
||||
MSR_CPSRf_i(0);
|
||||
RSB_rri(REG_WORK3, REG_WORK1, 9);
|
||||
UNSIGNED8_REG_2_REG(REG_WORK1, s);
|
||||
ORRS_rrrLSRr(d, REG_WORK2, REG_WORK1, REG_WORK3); // this LSR places correct bit in carry
|
||||
|
||||
// Duplicate carry
|
||||
MOV_ri(x, 1);
|
||||
CC_MOV_ri(NATIVE_CC_CC, x, 0);
|
||||
|
||||
// Calc N and Z
|
||||
BFI_rrii(d, x, 8, 8); // Make sure to set carry (last bit shifted out)
|
||||
LSLS_rri(REG_WORK1, d, 24);
|
||||
|
||||
// end of op
|
||||
|
||||
unlock2(x);
|
||||
unlock2(d);
|
||||
unlock2(s);
|
||||
unlock2(i);
|
||||
}
|
||||
MENDFUNC(3,jff_ROXL_b,(W4 d, RR4 s, RR4 i))
|
||||
|
||||
MIDFUNC(3,jff_ROXL_w,(W4 d, RR4 s, RR4 i))
|
||||
{
|
||||
i = readreg(i, 4);
|
||||
s = readreg(s, 4);
|
||||
int x = rmw(FLAGX, 4, 4);
|
||||
d = writereg(d, 4);
|
||||
|
||||
AND_rri(REG_WORK1, i, 63);
|
||||
CMP_ri(REG_WORK1, 33);
|
||||
CC_SUB_rri(NATIVE_CC_GT, REG_WORK1, REG_WORK1, 34);
|
||||
CMP_ri(REG_WORK1, 16);
|
||||
CC_SUB_rri(NATIVE_CC_GT, REG_WORK1, REG_WORK1, 17);
|
||||
TST_rr(REG_WORK1, REG_WORK1);
|
||||
BNE_i(3); // need to rotate
|
||||
|
||||
MSR_CPSRf_i(0);
|
||||
MOVS_rrLSLi(d, s, 16);
|
||||
LSR_rri(d, d, 16);
|
||||
B_i(12); // end of op
|
||||
|
||||
// need to rotate
|
||||
CMP_ri(REG_WORK1, 16);
|
||||
CC_MOV_rrLSLr(NATIVE_CC_NE, REG_WORK2, s, REG_WORK1);
|
||||
CC_MOV_ri(NATIVE_CC_EQ, REG_WORK2, 0);
|
||||
|
||||
SUB_rri(REG_WORK3, REG_WORK1, 1);
|
||||
ORR_rrrLSLr(REG_WORK2, REG_WORK2, x, REG_WORK3);
|
||||
|
||||
MSR_CPSRf_i(0);
|
||||
RSB_rri(REG_WORK3, REG_WORK1, 17);
|
||||
UNSIGNED16_REG_2_REG(REG_WORK1, s);
|
||||
ORRS_rrrLSRr(d, REG_WORK2, REG_WORK1, REG_WORK3); // this LSR places correct bit in carry
|
||||
|
||||
// Duplicate carry
|
||||
MOV_ri(x, 1);
|
||||
CC_MOV_ri(NATIVE_CC_CC, x, 0);
|
||||
|
||||
// Calc N and Z
|
||||
BFI_rrii(d, x, 16, 16); // Make sure to set carry (last bit shifted out)
|
||||
LSLS_rri(REG_WORK1, d, 16);
|
||||
|
||||
// end of op
|
||||
|
||||
unlock2(x);
|
||||
unlock2(d);
|
||||
unlock2(s);
|
||||
unlock2(i);
|
||||
}
|
||||
MENDFUNC(3,jff_ROXL_w,(W4 d, RR4 s, RR4 i))
|
||||
|
||||
MIDFUNC(3,jff_ROXL_l,(W4 d, RR4 s, RR4 i))
|
||||
{
|
||||
i = readreg(i, 4);
|
||||
s = readreg(s, 4);
|
||||
int x = rmw(FLAGX, 4, 4);
|
||||
d = writereg(d, 4);
|
||||
|
||||
AND_rri(REG_WORK1, i, 63);
|
||||
CMP_ri(REG_WORK1, 32);
|
||||
CC_SUB_rri(NATIVE_CC_GT, REG_WORK1, REG_WORK1, 33);
|
||||
TST_rr(REG_WORK1, REG_WORK1);
|
||||
BNE_i(2); // need to rotate
|
||||
|
||||
MSR_CPSRf_i(0);
|
||||
MOVS_rr(d, s);
|
||||
B_i(9); // end of op
|
||||
|
||||
// need to rotate
|
||||
CMP_ri(REG_WORK1, 32);
|
||||
CC_MOV_rrLSLr(NATIVE_CC_NE, REG_WORK2, s, REG_WORK1);
|
||||
CC_MOV_ri(NATIVE_CC_EQ, REG_WORK2, 0);
|
||||
|
||||
SUB_rri(REG_WORK3, REG_WORK1, 1);
|
||||
ORR_rrrLSLr(REG_WORK2, REG_WORK2, x, REG_WORK3);
|
||||
|
||||
MSR_CPSRf_i(0);
|
||||
RSB_rri(REG_WORK3, REG_WORK1, 33);
|
||||
ORRS_rrrLSRr(d, REG_WORK2, s, REG_WORK3); // this LSR places correct bit in carry
|
||||
|
||||
// Duplicate carry
|
||||
MOV_ri(x, 1);
|
||||
CC_MOV_ri(NATIVE_CC_CC, x, 0);
|
||||
|
||||
// end of op
|
||||
|
||||
unlock2(x);
|
||||
unlock2(d);
|
||||
unlock2(s);
|
||||
unlock2(i);
|
||||
}
|
||||
MENDFUNC(3,jff_ROXL_l,(W4 d, RR4 s, RR4 i))
|
||||
|
||||
|
|
@ -4266,8 +4681,7 @@ MIDFUNC(2,jff_ROXLW,(W4 d, RR4 s))
|
|||
LSL_rri(d, s, 1);
|
||||
ADC_rri(d, d, 0);
|
||||
MSR_CPSRf_i(0);
|
||||
LSLS_rri(d, d, 15);
|
||||
LSR_rri(d, d, 16);
|
||||
LSLS_rri(REG_WORK1, d, 16);
|
||||
|
||||
// Duplicate carry
|
||||
MOV_ri(x, 1);
|
||||
|
|
|
|||
|
|
@ -165,6 +165,12 @@ DECLARE_MIDFUNC(jff_DIVU(W4 d, RR4 s1, RR4 s2));
|
|||
DECLARE_MIDFUNC(jnf_DIVS(W4 d, RR4 s1, RR4 s2));
|
||||
DECLARE_MIDFUNC(jff_DIVS(W4 d, RR4 s1, RR4 s2));
|
||||
|
||||
// DIVL
|
||||
DECLARE_MIDFUNC(jnf_DIVLU32(RW4 d, RR4 s1, W4 rem));
|
||||
DECLARE_MIDFUNC(jff_DIVLU32(RW4 d, RR4 s1, W4 rem));
|
||||
DECLARE_MIDFUNC(jnf_DIVLS32(RW4 d, RR4 s1, W4 rem));
|
||||
DECLARE_MIDFUNC(jff_DIVLS32(RW4 d, RR4 s1, W4 rem));
|
||||
|
||||
// EOR
|
||||
DECLARE_MIDFUNC(jnf_EOR(W4 d, RR4 s, RR4 v));
|
||||
DECLARE_MIDFUNC(jff_EOR_b(W4 d, RR1 s, RR1 v));
|
||||
|
|
|
|||
|
|
@ -864,17 +864,17 @@ extern const struct comptbl op_smalltbl_0_comp_ff[] = {
|
|||
{ op_4c3a_0_comp_ff, 0x00000002, 19514 }, /* MULL */
|
||||
{ op_4c3b_0_comp_ff, 0x00000002, 19515 }, /* MULL */
|
||||
{ op_4c3c_0_comp_ff, 0x00000002, 19516 }, /* MULL */
|
||||
{ NULL, 0x00000001, 19520 }, /* DIVL */
|
||||
{ NULL, 0x00000001, 19536 }, /* DIVL */
|
||||
{ NULL, 0x00000001, 19544 }, /* DIVL */
|
||||
{ NULL, 0x00000001, 19552 }, /* DIVL */
|
||||
{ NULL, 0x00000001, 19560 }, /* DIVL */
|
||||
{ NULL, 0x00000001, 19568 }, /* DIVL */
|
||||
{ NULL, 0x00000001, 19576 }, /* DIVL */
|
||||
{ NULL, 0x00000001, 19577 }, /* DIVL */
|
||||
{ NULL, 0x00000001, 19578 }, /* DIVL */
|
||||
{ NULL, 0x00000001, 19579 }, /* DIVL */
|
||||
{ NULL, 0x00000001, 19580 }, /* DIVL */
|
||||
{ op_4c40_0_comp_ff, 0x00000002, 19520 }, /* DIVL */
|
||||
{ op_4c50_0_comp_ff, 0x00000002, 19536 }, /* DIVL */
|
||||
{ op_4c58_0_comp_ff, 0x00000002, 19544 }, /* DIVL */
|
||||
{ op_4c60_0_comp_ff, 0x00000002, 19552 }, /* DIVL */
|
||||
{ op_4c68_0_comp_ff, 0x00000002, 19560 }, /* DIVL */
|
||||
{ op_4c70_0_comp_ff, 0x00000002, 19568 }, /* DIVL */
|
||||
{ op_4c78_0_comp_ff, 0x00000002, 19576 }, /* DIVL */
|
||||
{ op_4c79_0_comp_ff, 0x00000002, 19577 }, /* DIVL */
|
||||
{ op_4c7a_0_comp_ff, 0x00000002, 19578 }, /* DIVL */
|
||||
{ op_4c7b_0_comp_ff, 0x00000002, 19579 }, /* DIVL */
|
||||
{ op_4c7c_0_comp_ff, 0x00000002, 19580 }, /* DIVL */
|
||||
{ op_4c90_0_comp_ff, 0x00000002, 19600 }, /* MVMEL */
|
||||
{ op_4c98_0_comp_ff, 0x00000002, 19608 }, /* MVMEL */
|
||||
{ op_4ca8_0_comp_ff, 0x00000002, 19624 }, /* MVMEL */
|
||||
|
|
@ -1667,27 +1667,27 @@ extern const struct comptbl op_smalltbl_0_comp_ff[] = {
|
|||
{ op_e0f9_0_comp_ff, 0x00000002, 57593 }, /* ASRW */
|
||||
{ op_e100_0_comp_ff, 0x00000000, 57600 }, /* ASL */
|
||||
{ op_e108_0_comp_ff, 0x00000000, 57608 }, /* LSL */
|
||||
{ NULL, 0x00000008, 57616 }, /* ROXL */
|
||||
{ op_e110_0_comp_ff, 0x00000008, 57616 }, /* ROXL */
|
||||
{ op_e118_0_comp_ff, 0x00000000, 57624 }, /* ROL */
|
||||
{ op_e120_0_comp_ff, 0x00000000, 57632 }, /* ASL */
|
||||
{ op_e128_0_comp_ff, 0x00000000, 57640 }, /* LSL */
|
||||
{ NULL, 0x00000008, 57648 }, /* ROXL */
|
||||
{ op_e130_0_comp_ff, 0x00000008, 57648 }, /* ROXL */
|
||||
{ op_e138_0_comp_ff, 0x00000000, 57656 }, /* ROL */
|
||||
{ op_e140_0_comp_ff, 0x00000000, 57664 }, /* ASL */
|
||||
{ op_e148_0_comp_ff, 0x00000000, 57672 }, /* LSL */
|
||||
{ NULL, 0x00000008, 57680 }, /* ROXL */
|
||||
{ op_e150_0_comp_ff, 0x00000008, 57680 }, /* ROXL */
|
||||
{ op_e158_0_comp_ff, 0x00000000, 57688 }, /* ROL */
|
||||
{ op_e160_0_comp_ff, 0x00000000, 57696 }, /* ASL */
|
||||
{ op_e168_0_comp_ff, 0x00000000, 57704 }, /* LSL */
|
||||
{ NULL, 0x00000008, 57712 }, /* ROXL */
|
||||
{ op_e170_0_comp_ff, 0x00000008, 57712 }, /* ROXL */
|
||||
{ op_e178_0_comp_ff, 0x00000000, 57720 }, /* ROL */
|
||||
{ op_e180_0_comp_ff, 0x00000000, 57728 }, /* ASL */
|
||||
{ op_e188_0_comp_ff, 0x00000000, 57736 }, /* LSL */
|
||||
{ NULL, 0x00000008, 57744 }, /* ROXL */
|
||||
{ op_e190_0_comp_ff, 0x00000008, 57744 }, /* ROXL */
|
||||
{ op_e198_0_comp_ff, 0x00000000, 57752 }, /* ROL */
|
||||
{ op_e1a0_0_comp_ff, 0x00000000, 57760 }, /* ASL */
|
||||
{ op_e1a8_0_comp_ff, 0x00000000, 57768 }, /* LSL */
|
||||
{ NULL, 0x00000008, 57776 }, /* ROXL */
|
||||
{ op_e1b0_0_comp_ff, 0x00000008, 57776 }, /* ROXL */
|
||||
{ op_e1b8_0_comp_ff, 0x00000000, 57784 }, /* ROL */
|
||||
{ op_e1d0_0_comp_ff, 0x00000000, 57808 }, /* ASLW */
|
||||
{ op_e1d8_0_comp_ff, 0x00000000, 57816 }, /* ASLW */
|
||||
|
|
@ -2736,17 +2736,17 @@ extern const struct comptbl op_smalltbl_0_comp_nf[] = {
|
|||
{ op_4c3a_0_comp_nf, 0x00000002, 19514 }, /* MULL */
|
||||
{ op_4c3b_0_comp_nf, 0x00000002, 19515 }, /* MULL */
|
||||
{ op_4c3c_0_comp_nf, 0x00000002, 19516 }, /* MULL */
|
||||
{ NULL, 0x00000001, 19520 }, /* DIVL */
|
||||
{ NULL, 0x00000001, 19536 }, /* DIVL */
|
||||
{ NULL, 0x00000001, 19544 }, /* DIVL */
|
||||
{ NULL, 0x00000001, 19552 }, /* DIVL */
|
||||
{ NULL, 0x00000001, 19560 }, /* DIVL */
|
||||
{ NULL, 0x00000001, 19568 }, /* DIVL */
|
||||
{ NULL, 0x00000001, 19576 }, /* DIVL */
|
||||
{ NULL, 0x00000001, 19577 }, /* DIVL */
|
||||
{ NULL, 0x00000001, 19578 }, /* DIVL */
|
||||
{ NULL, 0x00000001, 19579 }, /* DIVL */
|
||||
{ NULL, 0x00000001, 19580 }, /* DIVL */
|
||||
{ op_4c40_0_comp_nf, 0x00000002, 19520 }, /* DIVL */
|
||||
{ op_4c50_0_comp_nf, 0x00000002, 19536 }, /* DIVL */
|
||||
{ op_4c58_0_comp_nf, 0x00000002, 19544 }, /* DIVL */
|
||||
{ op_4c60_0_comp_nf, 0x00000002, 19552 }, /* DIVL */
|
||||
{ op_4c68_0_comp_nf, 0x00000002, 19560 }, /* DIVL */
|
||||
{ op_4c70_0_comp_nf, 0x00000002, 19568 }, /* DIVL */
|
||||
{ op_4c78_0_comp_nf, 0x00000002, 19576 }, /* DIVL */
|
||||
{ op_4c79_0_comp_nf, 0x00000002, 19577 }, /* DIVL */
|
||||
{ op_4c7a_0_comp_nf, 0x00000002, 19578 }, /* DIVL */
|
||||
{ op_4c7b_0_comp_nf, 0x00000002, 19579 }, /* DIVL */
|
||||
{ op_4c7c_0_comp_nf, 0x00000002, 19580 }, /* DIVL */
|
||||
{ op_4c90_0_comp_nf, 0x00000002, 19600 }, /* MVMEL */
|
||||
{ op_4c98_0_comp_nf, 0x00000002, 19608 }, /* MVMEL */
|
||||
{ op_4ca8_0_comp_nf, 0x00000002, 19624 }, /* MVMEL */
|
||||
|
|
@ -3539,27 +3539,27 @@ extern const struct comptbl op_smalltbl_0_comp_nf[] = {
|
|||
{ op_e0f9_0_comp_nf, 0x00000002, 57593 }, /* ASRW */
|
||||
{ op_e100_0_comp_nf, 0x00000000, 57600 }, /* ASL */
|
||||
{ op_e108_0_comp_nf, 0x00000000, 57608 }, /* LSL */
|
||||
{ NULL, 0x00000008, 57616 }, /* ROXL */
|
||||
{ op_e110_0_comp_nf, 0x00000008, 57616 }, /* ROXL */
|
||||
{ op_e118_0_comp_nf, 0x00000000, 57624 }, /* ROL */
|
||||
{ op_e120_0_comp_nf, 0x00000000, 57632 }, /* ASL */
|
||||
{ op_e128_0_comp_nf, 0x00000000, 57640 }, /* LSL */
|
||||
{ NULL, 0x00000008, 57648 }, /* ROXL */
|
||||
{ op_e130_0_comp_nf, 0x00000008, 57648 }, /* ROXL */
|
||||
{ op_e138_0_comp_nf, 0x00000000, 57656 }, /* ROL */
|
||||
{ op_e140_0_comp_nf, 0x00000000, 57664 }, /* ASL */
|
||||
{ op_e148_0_comp_nf, 0x00000000, 57672 }, /* LSL */
|
||||
{ NULL, 0x00000008, 57680 }, /* ROXL */
|
||||
{ op_e150_0_comp_nf, 0x00000008, 57680 }, /* ROXL */
|
||||
{ op_e158_0_comp_nf, 0x00000000, 57688 }, /* ROL */
|
||||
{ op_e160_0_comp_nf, 0x00000000, 57696 }, /* ASL */
|
||||
{ op_e168_0_comp_nf, 0x00000000, 57704 }, /* LSL */
|
||||
{ NULL, 0x00000008, 57712 }, /* ROXL */
|
||||
{ op_e170_0_comp_nf, 0x00000008, 57712 }, /* ROXL */
|
||||
{ op_e178_0_comp_nf, 0x00000000, 57720 }, /* ROL */
|
||||
{ op_e180_0_comp_nf, 0x00000000, 57728 }, /* ASL */
|
||||
{ op_e188_0_comp_nf, 0x00000000, 57736 }, /* LSL */
|
||||
{ NULL, 0x00000008, 57744 }, /* ROXL */
|
||||
{ op_e190_0_comp_nf, 0x00000008, 57744 }, /* ROXL */
|
||||
{ op_e198_0_comp_nf, 0x00000000, 57752 }, /* ROL */
|
||||
{ op_e1a0_0_comp_nf, 0x00000000, 57760 }, /* ASL */
|
||||
{ op_e1a8_0_comp_nf, 0x00000000, 57768 }, /* LSL */
|
||||
{ NULL, 0x00000008, 57776 }, /* ROXL */
|
||||
{ op_e1b0_0_comp_nf, 0x00000008, 57776 }, /* ROXL */
|
||||
{ op_e1b8_0_comp_nf, 0x00000000, 57784 }, /* ROL */
|
||||
{ op_e1d0_0_comp_nf, 0x00000000, 57808 }, /* ASLW */
|
||||
{ op_e1d8_0_comp_nf, 0x00000000, 57816 }, /* ASLW */
|
||||
|
|
|
|||
|
|
@ -703,6 +703,17 @@ extern compop_func op_4c39_0_comp_ff;
|
|||
extern compop_func op_4c3a_0_comp_ff;
|
||||
extern compop_func op_4c3b_0_comp_ff;
|
||||
extern compop_func op_4c3c_0_comp_ff;
|
||||
extern compop_func op_4c40_0_comp_ff;
|
||||
extern compop_func op_4c50_0_comp_ff;
|
||||
extern compop_func op_4c58_0_comp_ff;
|
||||
extern compop_func op_4c60_0_comp_ff;
|
||||
extern compop_func op_4c68_0_comp_ff;
|
||||
extern compop_func op_4c70_0_comp_ff;
|
||||
extern compop_func op_4c78_0_comp_ff;
|
||||
extern compop_func op_4c79_0_comp_ff;
|
||||
extern compop_func op_4c7a_0_comp_ff;
|
||||
extern compop_func op_4c7b_0_comp_ff;
|
||||
extern compop_func op_4c7c_0_comp_ff;
|
||||
extern compop_func op_4c90_0_comp_ff;
|
||||
extern compop_func op_4c98_0_comp_ff;
|
||||
extern compop_func op_4ca8_0_comp_ff;
|
||||
|
|
@ -1417,21 +1428,27 @@ extern compop_func op_e0f8_0_comp_ff;
|
|||
extern compop_func op_e0f9_0_comp_ff;
|
||||
extern compop_func op_e100_0_comp_ff;
|
||||
extern compop_func op_e108_0_comp_ff;
|
||||
extern compop_func op_e110_0_comp_ff;
|
||||
extern compop_func op_e118_0_comp_ff;
|
||||
extern compop_func op_e120_0_comp_ff;
|
||||
extern compop_func op_e128_0_comp_ff;
|
||||
extern compop_func op_e130_0_comp_ff;
|
||||
extern compop_func op_e138_0_comp_ff;
|
||||
extern compop_func op_e140_0_comp_ff;
|
||||
extern compop_func op_e148_0_comp_ff;
|
||||
extern compop_func op_e150_0_comp_ff;
|
||||
extern compop_func op_e158_0_comp_ff;
|
||||
extern compop_func op_e160_0_comp_ff;
|
||||
extern compop_func op_e168_0_comp_ff;
|
||||
extern compop_func op_e170_0_comp_ff;
|
||||
extern compop_func op_e178_0_comp_ff;
|
||||
extern compop_func op_e180_0_comp_ff;
|
||||
extern compop_func op_e188_0_comp_ff;
|
||||
extern compop_func op_e190_0_comp_ff;
|
||||
extern compop_func op_e198_0_comp_ff;
|
||||
extern compop_func op_e1a0_0_comp_ff;
|
||||
extern compop_func op_e1a8_0_comp_ff;
|
||||
extern compop_func op_e1b0_0_comp_ff;
|
||||
extern compop_func op_e1b8_0_comp_ff;
|
||||
extern compop_func op_e1d0_0_comp_ff;
|
||||
extern compop_func op_e1d8_0_comp_ff;
|
||||
|
|
@ -2194,6 +2211,17 @@ extern compop_func op_4c39_0_comp_nf;
|
|||
extern compop_func op_4c3a_0_comp_nf;
|
||||
extern compop_func op_4c3b_0_comp_nf;
|
||||
extern compop_func op_4c3c_0_comp_nf;
|
||||
extern compop_func op_4c40_0_comp_nf;
|
||||
extern compop_func op_4c50_0_comp_nf;
|
||||
extern compop_func op_4c58_0_comp_nf;
|
||||
extern compop_func op_4c60_0_comp_nf;
|
||||
extern compop_func op_4c68_0_comp_nf;
|
||||
extern compop_func op_4c70_0_comp_nf;
|
||||
extern compop_func op_4c78_0_comp_nf;
|
||||
extern compop_func op_4c79_0_comp_nf;
|
||||
extern compop_func op_4c7a_0_comp_nf;
|
||||
extern compop_func op_4c7b_0_comp_nf;
|
||||
extern compop_func op_4c7c_0_comp_nf;
|
||||
extern compop_func op_4c90_0_comp_nf;
|
||||
extern compop_func op_4c98_0_comp_nf;
|
||||
extern compop_func op_4ca8_0_comp_nf;
|
||||
|
|
@ -2908,21 +2936,27 @@ extern compop_func op_e0f8_0_comp_nf;
|
|||
extern compop_func op_e0f9_0_comp_nf;
|
||||
extern compop_func op_e100_0_comp_nf;
|
||||
extern compop_func op_e108_0_comp_nf;
|
||||
extern compop_func op_e110_0_comp_nf;
|
||||
extern compop_func op_e118_0_comp_nf;
|
||||
extern compop_func op_e120_0_comp_nf;
|
||||
extern compop_func op_e128_0_comp_nf;
|
||||
extern compop_func op_e130_0_comp_nf;
|
||||
extern compop_func op_e138_0_comp_nf;
|
||||
extern compop_func op_e140_0_comp_nf;
|
||||
extern compop_func op_e148_0_comp_nf;
|
||||
extern compop_func op_e150_0_comp_nf;
|
||||
extern compop_func op_e158_0_comp_nf;
|
||||
extern compop_func op_e160_0_comp_nf;
|
||||
extern compop_func op_e168_0_comp_nf;
|
||||
extern compop_func op_e170_0_comp_nf;
|
||||
extern compop_func op_e178_0_comp_nf;
|
||||
extern compop_func op_e180_0_comp_nf;
|
||||
extern compop_func op_e188_0_comp_nf;
|
||||
extern compop_func op_e190_0_comp_nf;
|
||||
extern compop_func op_e198_0_comp_nf;
|
||||
extern compop_func op_e1a0_0_comp_nf;
|
||||
extern compop_func op_e1a8_0_comp_nf;
|
||||
extern compop_func op_e1b0_0_comp_nf;
|
||||
extern compop_func op_e1b8_0_comp_nf;
|
||||
extern compop_func op_e1d0_0_comp_nf;
|
||||
extern compop_func op_e1d8_0_comp_nf;
|
||||
|
|
|
|||
|
|
@ -107,7 +107,7 @@
|
|||
//#define DISABLE_I_LSL
|
||||
//#define DISABLE_I_ROL
|
||||
//#define DISABLE_I_ROR
|
||||
#define DISABLE_I_ROXL
|
||||
//#define DISABLE_I_ROXL
|
||||
#define DISABLE_I_ROXR
|
||||
//#define DISABLE_I_ASRW
|
||||
//#define DISABLE_I_ASLW
|
||||
|
|
@ -125,6 +125,7 @@
|
|||
|
||||
//#define DISABLE_I_DIVU
|
||||
//#define DISABLE_I_DIVS
|
||||
//#define DISABLE_I_DIVL
|
||||
|
||||
|
||||
#define RETURN "return 0;"
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||||
|
|
@ -1300,6 +1301,47 @@ static void gen_divs(uae_u32 opcode, struct instr *curi, char* ssize) {
|
|||
genastore("tmp", curi->dmode, "dstreg", sz_long /*curi->size*/, "dst");
|
||||
}
|
||||
|
||||
static void gen_divl(uae_u32 opcode, struct instr *curi, char* ssize) {
|
||||
(void) opcode;
|
||||
(void) ssize;
|
||||
comprintf("\t dont_care_flags();\n");
|
||||
comprintf("\t uae_u16 extra=%s;\n", gen_nextiword());
|
||||
comprintf("\t int r2=(extra>>12)&7;\n");
|
||||
comprintf("\t int r3=extra&7;\n");
|
||||
genamode(curi->dmode, "dstreg", curi->size, "dst", 1, 0);
|
||||
comprintf("\tregister_possible_exception();\n");
|
||||
|
||||
if (!noflags) {
|
||||
comprintf("\t if (extra & 0x0400) {\n"); /* Need full 64 bit divisor */
|
||||
comprintf("\t FAIL(1);\n");
|
||||
comprintf("\t m68k_pc_offset=m68k_pc_offset_thisinst;\n");
|
||||
comprintf("\t " RETURN "\n");
|
||||
comprintf("\t } else { \n");
|
||||
/* operands in src and r2, result goes into r2, remainder into r3 */
|
||||
/* s2 = s2 / src */
|
||||
/* s3 = s2 % src */
|
||||
comprintf("\t if (extra & 0x0800) { \n"); /* signed */
|
||||
comprintf("\t jff_DIVLS32(r2,dst,r3);\n");
|
||||
comprintf("\t } else { \n");
|
||||
comprintf("\t\t jff_DIVLU32(r2,dst,r3);\n");
|
||||
comprintf("\t } \n");
|
||||
comprintf("\t }\n");
|
||||
comprintf("\t live_flags();\n");
|
||||
} else {
|
||||
comprintf("\t if (extra & 0x0400) {\n"); /* Need full 64 bit divisor */
|
||||
comprintf("\t FAIL(1);\n");
|
||||
comprintf("\t m68k_pc_offset=m68k_pc_offset_thisinst;\n");
|
||||
comprintf("\t " RETURN "\n");
|
||||
comprintf("\t } else {\n");
|
||||
comprintf("\t if (extra & 0x0800) { \n"); /* signed */
|
||||
comprintf("\t jnf_DIVLS32(r2,dst,r3);\n");
|
||||
comprintf("\t } else { \n");
|
||||
comprintf("\t\t jnf_DIVLU32(r2,dst,r3);\n");
|
||||
comprintf("\t } \n");
|
||||
comprintf("\t }\n");
|
||||
}
|
||||
}
|
||||
|
||||
static void gen_eor(uae_u32 opcode, struct instr *curi, char* ssize) {
|
||||
(void) opcode;
|
||||
genamode(curi->smode, "srcreg", curi->size, "src", 1, 0);
|
||||
|
|
@ -1538,7 +1580,6 @@ static void gen_mull(uae_u32 opcode, struct instr *curi, char* ssize) {
|
|||
comprintf("\t } \n"); /* The result is in r2/r3, with r2 holding the lower 32 bits */
|
||||
comprintf("\t } else {\n"); /* Only want 32 bit result */
|
||||
/* operands in dst and r2, result goes into r2 */
|
||||
/* shouldn't matter whether it's signed or unsigned?!? */
|
||||
comprintf("\t if (extra & 0x0800) { \n"); /* signed */
|
||||
comprintf("\t jff_MULS32(r2,dst);\n");
|
||||
comprintf("\t } else { \n");
|
||||
|
|
@ -1557,7 +1598,6 @@ static void gen_mull(uae_u32 opcode, struct instr *curi, char* ssize) {
|
|||
comprintf("\t } \n"); /* The result is in r2/r3, with r2 holding the lower 32 bits */
|
||||
comprintf("\t } else {\n"); /* Only want 32 bit result */
|
||||
/* operands in dst and r2, result foes into r2 */
|
||||
/* shouldn't matter whether it's signed or unsigned?!? */
|
||||
comprintf("\t if (extra & 0x0800) { \n"); /* signed */
|
||||
comprintf("\t jnf_MULS32(r2,dst);\n");
|
||||
comprintf("\t } else { \n");
|
||||
|
|
@ -2716,8 +2756,10 @@ gen_opcode(unsigned long int opcode) {
|
|||
break;
|
||||
|
||||
case i_DIVL:
|
||||
isjump;
|
||||
#ifdef DISABLE_I_DIVL
|
||||
failure;
|
||||
#endif
|
||||
gen_divl(opcode, curi, ssize);
|
||||
break;
|
||||
|
||||
case i_MULL:
|
||||
|
|
@ -3043,7 +3085,7 @@ generate_one_opcode(int rp, int noflags)
|
|||
dmsk = 7;
|
||||
|
||||
next_cpu_level = -1;
|
||||
if (table68k[opcode].mnemo == i_DIVU || table68k[opcode].mnemo == i_DIVS) {
|
||||
if (table68k[opcode].mnemo == i_DIVU || table68k[opcode].mnemo == i_DIVS || table68k[opcode].mnemo == i_DIVL) {
|
||||
comprintf("#ifndef ARMV6T2\n");
|
||||
comprintf(" FAIL(1);\n");
|
||||
comprintf(" " RETURN "\n");
|
||||
|
|
@ -3141,7 +3183,7 @@ generate_one_opcode(int rp, int noflags)
|
|||
if (global_fpu) flags |= 32;
|
||||
|
||||
comprintf ("return 0;\n");
|
||||
if (table68k[opcode].mnemo == i_DIVU || table68k[opcode].mnemo == i_DIVS) {
|
||||
if (table68k[opcode].mnemo == i_DIVU || table68k[opcode].mnemo == i_DIVS || table68k[opcode].mnemo == i_DIVL) {
|
||||
comprintf("#endif\n");
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue