Unknown W. Brackets
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9b2fa46861
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IR: Add mini native jit MIPS block profiler.
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2023-09-24 23:04:29 -07:00 |
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Unknown W. Brackets
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e02426cbbf
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arm64jit: Implement some system ops.
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2023-09-03 21:16:08 -07:00 |
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Unknown W. Brackets
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6a75e6712e
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riscv: Use automapping for special cases too.
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2023-08-20 12:42:11 -07:00 |
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Unknown W. Brackets
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cc4bc406d5
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riscv: Cleanup VfpuCtrlToReg meta, use auto-map.
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2023-08-20 12:42:11 -07:00 |
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Unknown W. Brackets
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e40ae60029
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riscv: Mark normalized32 after mapping.
It's less confusing to separate it.
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2023-08-20 12:42:11 -07:00 |
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Unknown W. Brackets
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f9bf7de701
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riscv: Use a single reg cache.
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2023-08-20 12:42:11 -07:00 |
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Unknown W. Brackets
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a23ade8f75
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riscv: Map IR regs based on metadata.
Only doing this in places without GPR/FPR mix or FPR/Vec overlap for now.
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2023-08-20 12:42:11 -07:00 |
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Unknown W. Brackets
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718a1b3944
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riscv: Centralize MarkDirty flagging.
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2023-08-19 16:15:49 -07:00 |
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Unknown W. Brackets
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4e41f83ecc
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riscv: Centralize IR reg cache metadata checks.
These are all largely the same between backends.
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2023-08-17 23:03:31 -07:00 |
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Unknown W. Brackets
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2b36e0a625
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irjit: ZeroFpCond -> FpCondFromReg.
We already have a zero reg, so this is more useful and symmetrical.
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2023-08-13 10:40:47 -07:00 |
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Unknown W. Brackets
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4b9011e475
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riscv: Reduce call bloat using temps.
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2023-08-08 23:17:32 -07:00 |
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Unknown W. Brackets
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93e3d35f5d
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irjit: Move more to IRNativeBackend, split.
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2023-08-06 00:16:43 -07:00 |
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Unknown W. Brackets
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a5671bc716
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riscv: Add simple debug log of missed ops.
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2023-07-30 00:02:10 -07:00 |
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Unknown W. Brackets
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6d4fb949c2
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riscv: Implement float compare ops.
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2023-07-29 19:02:15 -07:00 |
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Unknown W. Brackets
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23e9dffc68
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riscv: Implement vec4 shuffle and init.
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2023-07-25 20:33:56 -07:00 |
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Unknown W. Brackets
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df313bd296
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riscv: Fix rounding mode setting.
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2023-07-25 20:33:56 -07:00 |
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Unknown W. Brackets
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05360d5c7a
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riscv: Implement simplest float ops.
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2023-07-25 20:33:56 -07:00 |
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Unknown W. Brackets
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7071884a47
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riscv: Handle rounding mode and ctrl transfers.
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2023-07-25 20:33:56 -07:00 |
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Unknown W. Brackets
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a8edf5fa24
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riscv: Reduce bloat in jit fallbacks.
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2023-07-25 19:42:04 -07:00 |
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Unknown W. Brackets
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4100767b5e
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riscv: Optimize SetConst a bit.
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2023-07-23 18:01:00 -07:00 |
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Unknown W. Brackets
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34bfe93ea5
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riscv: Fix block lookup issues.
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2023-07-23 18:01:00 -07:00 |
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Unknown W. Brackets
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c2da7d18bb
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riscv: Stub out more IR compilation categories.
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2023-07-23 18:01:00 -07:00 |
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Unknown W. Brackets
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bf7a6eb2cd
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riscv: Add jit for some initial instructions.
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2023-07-23 18:01:00 -07:00 |
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